參數(shù)資料
型號(hào)： AD9220ARS-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 2/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 10MSPS 28-SSOP
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 12
采樣率（每秒）： 10M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 7
功率耗散（最大）： 310mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)單端，單極；1 個(gè)差分，單極
REV. E
–10–
AD9221/AD9223/AD9220
The addition of a differential input structure gives the user an
additional level of flexibility that is not possible with traditional
flash converters. The input stage allows the user to easily config-
ure the inputs for either single-ended operation or differential
operation. The A/D’s input structure allows the dc offset of the
input signal to be varied independently of the input span of the
converter. Specifically, the input to the A/D core is the differ-
ence of the voltages applied at the VINA and VINB input
pins. Therefore, the equation,
VVINA VINB
CORE
=
–
(1)
defines the output of the differential input stage and provides
the input to the A/D core.
The voltage, VCORE, must satisfy the condition,
–VREF
V
VREF
CORE
≤≤
(2)
where VREF is the voltage at the VREF pin.
While an infinite combination of VINA and VINB inputs exist
that satisfy Equation 2, there is an additional limitation placed
on the inputs by the power supply voltages of the AD9221/
AD9223/AD9220. The power supplies bound the valid operat-
ing range for VINA and VINB. The condition,
AVSS
V
VINA
AVDD
V
AVSS
V
VINB
AVDD
V
–.
.
–.
.
03
<<
+
<<
+
(3)
where AVSS is nominally 0 V and AVDD is nominally 5 V,
defines this requirement. Thus, the range of valid inputs for
VINA and VINB is any combination that satisfies both
Equations 2 and 3.
For additional information showing the relationship between
VINA, VINB, VREF and the digital output of the AD9221/
AD9223/AD9220, see Table IV.
Refer to Table I and Table II at the end of this section for a
summary of both the various analog input and reference con-
figurations.
ANALOG INPUT OPERATION
Figure 5 shows the equivalent analog input of the AD9221/
AD9223/AD9220, which consists of a differential sample-and-
hold amplifier (SHA). The differential input structure of the
SHA is highly flexible, allowing the devices to be easily config-
ured for either a differential or single-ended input. The dc
offset, or common-mode voltage, of the input(s) can be set to
accommodate either single-supply or dual-supply systems. Also,
note that the analog inputs, VINA and VINB, are interchange-
able with the exception that reversing the inputs to the VINA
and VINB pins results in a polarity inversion.
CS
QS1
QH1
VINA
VINB
CS
QS1
CPIN–
CPAR
CPIN+
CPAR
QS2
CH
QS2
CH
Figure 5. AD9221/AD9223/AD9220 Simplified Input Circuit
The SHA’s optimum distortion performance for a differential or
single-ended input is achieved under the following two conditions:
(1) the common-mode voltage is centered around midsupply
(i.e., AVDD/2 or approximately 2.5 V) and (2) the input signal
voltage span of the SHA is set at its lowest (i.e., 2 V input span).
This is due to the sampling switches, QS1, being CMOS switches
whose RON resistance is very low but has some signal depen-
dency that causes frequency dependent ac distortion while the
SHA is in the track mode. The RON resistance of a CMOS
switch is typically lowest at its midsupply but increases symmetri-
cally as the input signal approaches either AVDD or AVSS. A
lower input signal voltage span centered at midsupply reduces
the degree of RON modulation.
Figure 6 compares the AD9221/AD9223/AD9220’s THD vs.
frequency performance for a 2 V input span with a common-
mode voltage of 1 V and 2.5 V. Note how each A/D with a
common-mode voltage of 1 V exhibits a similar degradation in
THD performance at higher frequencies (i.e., beyond 750 kHz).
Similarly, note how the THD performance at lower frequencies
becomes less sensitive to the common-mode voltage. As the
input frequency approaches dc, the distortion will be dominated
by static nonlinearities such as INL and DNL. It is important to
note that these dc static nonlinearities are independent of any
RON modulation.
FREQUENCY – MHz
–90
0.1
10
1
THD
–
dB
–80
–70
–60
–50
AD9221
1VCM
AD9220
1VCM
AD9223
1VCM
AD9223
2.5VCM
AD9221
2.5VCM
AD9220
2.5VCM
Figure 6. AD9221/AD9223/AD9220 THD vs. Frequency for
VCM = 2.5 V and 1.0 V (AIN = –0.5 dB, Input Span = 2.0 V p-p)
Due to the high degree of symmetry within the SHA topology, a
significant improvement in distortion performance for differen-
tial input signals with frequencies up to and beyond Nyquist can
be realized. This inherent symmetry provides excellent cancella-
tion of both common-mode distortion and noise. Also, the
required input signal voltage span is reduced by a half, which
further reduces the degree of RON modulation and its effects
on distortion.
The optimum noise and dc linearity performance for either
differential or single-ended inputs is achieved with the largest
input signal voltage span (i.e., 5 V input span) and matched
input impedance for VINA and VINB. Note that only a slight
degradation in dc linearity performance exists between the 2 V
and 5 V input span as specified in the AD9221/AD9223/
AD9220 DC Specifications.
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