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    參數(shù)資料
    型號(hào): AD9219ABCPZRL7-40
    廠商: Analog Devices Inc
    文件頁(yè)數(shù): 24/56頁(yè)
    文件大小: 0K
    描述: IC ADC 10BIT SRL 40MSPS 64LFCSP
    標(biāo)準(zhǔn)包裝: 750
    位數(shù): 10
    采樣率(每秒): 40M
    數(shù)據(jù)接口: 串行,SPI?
    轉(zhuǎn)換器數(shù)目: 4
    功率耗散(最大): 313mW
    電壓電源: 模擬和數(shù)字
    工作溫度: -40°C ~ 85°C
    安裝類型: 表面貼裝
    封裝/外殼: 48-VFQFN 裸露焊盤,CSP
    供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
    包裝: 帶卷 (TR)
    輸入數(shù)目和類型: 8 個(gè)單端,單極;4 個(gè)差分,單極
    AD9219
    Data Sheet
    Rev. E | Page 30 of 56
    Internal Reference Operation
    A comparator within the AD9219 detects the potential at the
    SENSE pin and configures the reference. If SENSE is grounded,
    the reference amplifier switch is connected to the internal
    resistor divider (see Figure 64), setting VREF to 1 V.
    The REFT and REFB pins establish the input span of the ADC
    core from the reference configuration. The analog input full-
    scale range of the ADC equals twice the voltage of the reference
    pin for either an internal or an external reference configuration.
    If the reference of the AD9219 is used to drive multiple
    converters to improve gain matching, the loading of the refer-
    ence by the other converters must be considered. Figure 66
    depicts how the internal reference voltage is affected by loading.
    1F
    0.1F
    VREF
    SENSE
    0.5V
    REFT
    0.1F
    2.2F
    0.1F
    REFB
    SELECT
    LOGIC
    ADC
    CORE
    +
    VIN – x
    VIN + x
    05
    726
    -01
    0
    Figure 64. Internal Reference Configuration
    1F
    0.1F
    VREF
    0.5V
    REFT
    0.1F
    2.2F
    0.1F
    REFB
    SELECT
    LOGIC
    ADC
    CORE
    +
    VIN – x
    VIN + x
    SENSE
    R2
    R1
    05
    72
    6-
    0
    11
    Figure 65. External Reference Operation
    External Reference Operation
    The use of an external reference may be necessary to enhance
    the gain accuracy of the ADC or to improve thermal drift charac-
    teristics. Figure 67 shows the typical drift characteristics of the
    internal reference in 1 V mode.
    When the SENSE pin is tied to AVDD, the internal reference is
    disabled, allowing the use of an external reference. The external
    reference is loaded with an equivalent 6 kΩ load. An internal
    reference buffer generates the positive and negative full-scale
    references, REFT and REFB, for the ADC core. Therefore, the
    external reference must be limited to a nominal 1.0 V.
    01.0
    0.5
    2.0
    1.5
    3.0
    2.5
    3.5
    V
    RE
    F
    E
    RRO
    R
    (
    %
    )
    CURRENT LOAD (mA)
    057
    26
    -08
    3
    –30
    –5
    –10
    –15
    –20
    –25
    5
    0
    Figure 66. VREF Accuracy vs. Load
    0.02
    –0.18
    –40
    80
    60
    40
    20
    0
    –20
    TEMPERATURE (°C)
    V
    REF
    E
    R
    RO
    R
    (
    %
    )
    0
    –0.02
    –0.04
    –0.06
    –0.08
    –0.10
    –0.12
    –0.14
    –0.16
    05
    72
    6-
    0
    81
    Figure 67. Typical VREF Drift
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