參數(shù)資料
型號(hào)： AD9219-65EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/56頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD9219
設(shè)計(jì)資源： AD9219/28/59/87 Gerber Files
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 4
位數(shù)： 10
采樣率（每秒）： 40M
數(shù)據(jù)接口： 串行
輸入范圍： 2 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 378mW @ 1.8V
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9219
已供物品： 板
Data Sheet
AD9219
Rev. E | Page 23 of 56
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9219 sample clock inputs
(CLK+ and CLK) should be clocked with a differential signal.
This signal is typically ac-coupled to the CLK+ and CLK pins
via a transformer or capacitors. These pins are biased internally
and require no additional biasing.
Figure 52 shows a preferred method for clocking the AD9219. The
low jitter clock source is converted from a single-ended signal
to a differential signal using an RF transformer. The back-to-
back Schottky diodes across the secondary transformer limit
clock excursions into the AD9219 to approximately 0.8 V p-p
differential. This helps prevent the large voltage swings of the
clock from feeding through to other portions of the AD9219,
and it preserves the fast rise and fall times of the signal, which
are critical to low jitter performance.
0.1F
SCHOTTKY
DIODES:
HSM2812
CLK+
50
100
CLK–
CLK+
ADC
AD9219
Mini-Circuits
ADT1-1WT, 1:1Z
XFMR
05
72
6-
0
24
Figure 52. Transformer-Coupled Differential Clock
Another option is to ac-couple a differential PECL signal to the
sample clock input pins as shown in Figure 53. The AD9510/
drivers offers excellent jitter performance.
100
0.1F
240
50*
50*
CLK
*50 RESISTORS ARE OPTIONAL
CLK–
CLK+
ADC
AD9219
05
72
6
-02
5
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
PECL DRIVER
CLK+
CLK–
Figure 53. Differential PECL Sample Clock
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
100
0.1F
50*
CLK
*50 RESISTORS ARE OPTIONAL
CLK–
CLK+
ADC
AD9219
05
72
6-
0
26
LVDS DRIVER
CLK+
CLK–
Figure 54. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be driven directly from a CMOS gate, and the
CLK pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 55). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is designed
to withstand input voltages of up to 3.3 V and therefore offers
several selections for the drive logic voltage.
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
0.1F
39k
50*
OPTIONAL
100
0.1F
CLK
*50 RESISTOR IS OPTIONAL
CLK–
CLK+
ADC
AD9219
05
72
6-
0
27
CLK
CMOS DRIVER
CLK+
Figure 55. Single-Ended 1.8 V CMOS Sample Clock
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
0.1F
50*
CLK
*50 RESISTOR IS OPTIONAL
0.1F
CLK–
CLK+
ADC
AD9219
05
72
6-
0
28
CLK
OPTIONAL
100
CMOS DRIVER
CLK+
Figure 56. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9219 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9219. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. However,
some applications may require the DCS function to be off. If so,
keep in mind that the dynamic range performance can be affected
when operated in this mode. See the Memory Map section for
more details on using this feature.
Jitter in the rising edge of the input is an important concern, and it
is not reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates of less than
20 MHz nominal. The loop has a time constant associated with
it that must be considered in applications where the clock rate
can change dynamically. This requires a wait time of 1.5 μs to
5 μs after a dynamic clock frequency increase (or decrease)
before the DCS loop is relocked to the input signal. During the
period that the loop is not locked, the DCS loop is bypassed and
the internal device timing is dependent on the duty cycle of the
input clock signal. In such applications, it may be appropriate to
disable the duty cycle stabilizer. In all other applications, enabling
the DCS circuit is recommended to maximize ac performance.
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