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參數(shù)資料
| 型號(hào)： | AD9216-80 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit, 65/80/105 MSPS Dual A/D Converter |
| 中文描述： | 10位，65/80/105 MSPS雙通道的A / D轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 3/20頁(yè) |
| 文件大小： | 298K |
| 代理商： | AD9216-80 |
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Preliminary Technical Data
AD9216
AD9216–SPECIFICATIONS
DC SPECIFICATIONS
Table 1. (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = -0.5 dBFS Differential Input, 1.0 V
Internal Reference, TMIN to TMAX, unless otherwise noted.)
Test
AD9216BCP-65/80
Parameter
Temp
Level
Min
RESOLUTION
Full
VI
10
ACCURACY
No Missing Codes Guaranteed
Full
VI
10
Offset Error
Full
VI
Gain Error
1
Full
IV
Differential Nonlinearity (DNL)
2
Full
V
25°C
I
Integral Nonlinearity (INL)
2
Full
V
25°C
I
TEMPERATURE DRIFT
Offset Error
Full
V
Gain Error
1
Full
V
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Full
VI
Load Regulation @ 1.0 mA
Full
V
Output Voltage Error (0.5 V Mode)
Full
V
Load Regulation @ 0.5 mA
Full
V
INPUT REFERRED NOISE
Input Span = 1 V
25°C
V
Input Span = 2.0 V
25°C
V
ANALOG INPUT
Input Span = 1.0 V
Full
IV
Input Span = 2.0 V
Full
IV
Input Capacitance
3
Full
V
REFERENCE INPUT RESISTANCE
Full
V
POWER SUPPLIES
Supply Voltages
AVDD
Full
IV
2.7
DRVDD
Full
IV
2.25
Supply Current
IAVDD
2
Full
V
IDRVDD
2
Full
V
PSRR
Full
V
POWER CONSUMPTION
DC Input
4
Full
V
Sine Wave Input
2
Full
VI
Standby Power
5
Full
V
MATCHING CHARACTERISTICS
Offset Error
Full
V
Gain Error
Full
V
Rev. PrD
Page 3 of 20
6/15/2004
AD9216BCP-105
Min
Typ
10
10
±0.30
±1.0
±0.5
±0.5
±0.5
±0.5
±15
±30
±5
0.8
±2.5
0.1
0.8
0.4
1
2
2
7
2.7
3.0
2.25
2.5
TBD
TBD
±0.01
TBD
280
1
±0.1
±0.05
Unit
Bits
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
mV
mV
mV
mV
LSB rms
LSB rms
V p-p
V p-p
pF
k
V
V
mA
mA
% FSR
mW
mW
mW
% FSR
% FSR
Typ
±0.3
±1.0
±0.5
±0.5
±0.5
±0.5
±15
±30
±5
0.8
±2.5
0.1
0.8
0.4
1
2
2
7
3.0
2.5
TBD/TBD
TBD/TBD
±0.01
TBD/TBD
215/238
1/1
±0.1
±0.05
Max
±TBD
±TBD
±TBD
±TBD
±35
3.3
3.6
Max
±TBD
±TBD
±TBD
±TBD
±35
3.3
3.6
1
Gain error and gain temperature coefficient are based on the A/D converter only (with a fixed 1.0 V external reference).
2
Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure xx for the equivalent analog input
structure.
4
Measured with dc input at maximum clock rate.
5
Standby power is measured with the CLK_A and CLK_B pins inactive (i.e., set to AVDD or AGND).
Specifications subject to change without notice.
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