參數(shù)資料
型號(hào): AD9216-65PCB
廠商: Analog Devices, Inc.
英文描述: 10-Bit, 65/80/105 MSPS Dual A/D Converter
中文描述: 10位,65/80/105 MSPS雙通道的A / D轉(zhuǎn)換器
文件頁(yè)數(shù): 4/20頁(yè)
文件大?。?/td> 298K
代理商: AD9216-65PCB
AD9216
Preliminary Technical Data
DC SPECIFICATIONS (CONTINUED)
Table 2. (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = -0.5 dBFS Differential Input, 1.0 V
Internal Reference, TMIN to TMAX, unless otherwise noted.)
Test
AD9216BCP-65/80
Parameter
Temp
Level
Min
Typ
LOGIC INPUTS
High Level Input Voltage
Full
IV
2.0
Low Level Input Voltage
Full
IV
High Level Input Current
Full
IV
- 10
Low Level Input Current
Full
IV
- 10
Input Capacitance
Full
IV
2
LOGIC OUTPUTS
1
DRVDD = 2.5V
High Level Output
Voltage
Low Level Output Voltage
Full
IV
Rev. PrD
Page 4 of 20
6/15/2004
AD9216BCP-105
Min
Typ
2.0
- 10
- 10
2
2.45
Unit
V
V
μA
μA
pF
V
Max
0.8
+10
+10
Max
0.8
+10
+10
Full
IV
2.45
0.05
0.05
V
1
Output Voltage Levels measured with 5 pF load on each output.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
Table 3. Switching Specifications
Parameter
SWITCHING PERFORMANCE
Max Conversion Rate
Min Conversion Rate
CLK Period
CLK Pulsewidth High
1
CLK Pulsewidth Low
1
DATA OUTPUT PARAMETER
Output Delay
2
(t
PD
)
Pipeline Delay (Latency)
Aperture Delay (t
A
)
Aperture Uncertainty (t
J
)
Wake-Up Time
3
OUT-OF-RANGE RECOVERY
TIME
1
The AD9216 has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see TPC xx).
2
Output delay is measured from CLOCK 50% transition to DATA 50% transition, with a 5 pF load on each output.
3
Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
Specifications subject to change without notice.
N+1
N+2
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test
Level
VI
V
V
V
V
VI
V
V
V
V
V
AD9216BCP-65/80
Min
65/80
15.4/12.2
6.2/5
6.2/5
2.0
AD9216BCP-105
Min
Typ
105
9.5
4.2
4.2
2.0
4.8
6
1.0
0.5
2.5
2
Unit
MSPS
MSPS
ns
ns
ns
ns
Cycles
ns
ps rms
ms
Typ
4.8
6
1.0
0.5
2.5
2
Max
1
6.0
Max
1
6.0
t
A
t
PD
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N-1
N
N+1
ANALOG
INPUT
CLK
DATA
OUT
N–1
N
N+3
N+4
N+5
N+6
N+7
N+8
Figure 2. Timing Diagram
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