參數(shù)資料
型號： AD9204BCPZ-20
廠商： Analog Devices Inc
文件頁數(shù)： 17/36頁
文件大?。?/td> 0K
描述： IC ADC 10BIT 20MSPS DL 64LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 10
采樣率（每秒）： 20M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 69.5mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
輸入數(shù)目和類型： 4 個單端，單極；2 個差分，單極
產(chǎn)品目錄頁面： 780 (CN2011-ZH PDF)
AD9204
Rev. 0 | Page 24 of 36
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 52. The AD9510/AD9511/AD9512/
excellent jitter performance.
100
0.1F
240
50k
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
ADC
AD951x
PECL DRIVER
0
812
2-
01
9
Figure 52. Differential PECL Sample Clock (Up to 625 MHz)
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 53. The AD9510/
clock drivers offer excellent jitter performance.
100
0.1F
50k
CLK–
CLK+
ADC
CLOCK
INPUT
CLOCK
INPUT
AD951x
LVDS DRIVER
0
812
2-
020
Figure 53. Differential LVDS Sample Clock (Up to 625 MHz)
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK pin to ground with a 0.1 μF capacitor (see
OPTIONAL
100
0.1F
501
150 RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
VCC
1k
CLOCK
INPUT
AD951x
CMOS DRIVER
08
12
2-
02
1
Figure 54. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
Input Clock Divider
The AD9204 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8.
Optimum performance can be obtained by enabling the
internal duty cycle stabilizer (DCS) when using divide ratios
other than 1, 2, or 4.
The AD9204 clock divider can be synchronized using the
external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow
the clock divider to be resynchronized on every SYNC signal
or only on the first SYNC signal after the register is written. A
valid SYNC causes the clock divider to reset to its initial state.
This synchronization feature allows multiple parts to have their
clock dividers aligned to guarantee simultaneous input
sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9204 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9204. Noise and distortion perform-
ance are nearly flat for a wide range of duty cycles with the DCS
on, as shown in Figure 55.
Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 μs to 5 μs
is required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal.
80
75
70
65
60
55
50
40
45
10
20
30
40
50
60
70
80
POSITIVE DUTY CYCLE (%)
SN
R
(
d
B
F
S
)
08
12
2-
0
53
DCS ON
DCS OFF
Figure 55. SNR vs. DCS On/Off
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