參數資料
型號: AD9204-20EBZ
廠商: Analog Devices Inc
文件頁數: 16/36頁
文件大?。?/td> 0K
描述: BOARD EVALUATION 20MSPS AD9204
設計資源: AD9650,92xx Schematic
AD92xx/AD9650 Gerber Files
標準包裝: 1
ADC 的數量: 2
位數: 10
采樣率(每秒): 20M
數據接口: 串行,SPI?
輸入范圍: 1 ~ 2 Vpp
在以下條件下的電源(標準): 76.7mW @ 20MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9204
已供物品:
AD9204
Rev. 0 | Page 23 of 36
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 48 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
V
RE
F
E
RRO
R
(m
V
)
08
122
-05
2
VREF ERROR (mV)
Figure 48. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 37). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9204 sample clock
inputs, CLK+ and CLK, with a differential signal. The signal
is typically ac-coupled into the CLK+ and CLK pins via a
transformer or capacitors. These pins are biased internally
(see Figure 49) and require no external bias.
0.9V
AVDD
2pF
CLK–
CLK+
08
12
2-
0
16
Figure 49. Equivalent Clock Input Circuit
Clock Input Options
The AD9204 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter
is of the most concern, as described in the Jitter Considerations
section.
Figure 50 and Figure 51 show two preferred methods for clocking
the AD9204 (at clock rates up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF transformer or an RF balun.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is recom-
mended for clock frequencies from 10 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary limit clock excursions into the AD9204 to approx-
imately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9204 while
preserving the fast rise and fall times of the signal that are critical
to a low jitter performance.
0.1F
SCHOTTKY
DIODES:
HSMS2822
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
Mini-Circuits
ADT1-1WT, 1:1 Z
XFMR
08
12
2-
0
17
Figure 50. Transformer-Coupled Differential Clock (Up to 200 MHz)
0.1F
1nF
CLOCK
INPUT
1nF
50
CLK–
CLK+
SCHOTTKY
DIODES:
HSMS2822
ADC
08
12
2-
01
8
Figure 51. Balun-Coupled Differential Clock (Up to 625 MHz)
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