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參數資料
| 型號： | AD9101AE |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | 125 MSPS Monolithic Sampling Amplifier |
| 中文描述： | TRACK AND HOLD AMPLIFIER, CQCC20 |
| 封裝： | CERAMIC, LCC-20 |
| 文件頁數： | 4/12頁 |
| 文件大?。?/td> | 247K |
| 代理商： | AD9101AE |
AD9101
–4–
REV. 0
Acquisition T ime
is the amount of time it takes the AD9101
to reacquire the analog input when switching from hold to track
mode. T he interval starts at the 50% clock transition point and
ends when the input signal is reacquired to within a specified
error band at the hold capacitor.
Aperture Delay
establishes when the input signal is actually
sampled. It is the time difference between the analog propaga-
tion delay of the front-end buffer and the control switch delay
time (the time from the hold command transition to when the
switch is opened). For the AD9101, this is a negative value,
meaning that the analog delay is longer than the switch delay.
Aperture Jitter
is the random variation in the aperture delay.
T his is measured in ps-rms and is manifested as phase noise on
the held signal.
Droop Rate
is the change in output voltage as a function of
time (dV/dt). It is measured at the AD9101 output with the de-
vice in hold mode and the input held at a specified dc value; the
measurement starts immediately after the T /H switches from
track to hold.
Feedthrough Rejection
is the ratio of the output signal to the
input signal when in hold mode. T his is a measure of how well
the switch isolates the input signal from feeding through to the
output.
Hold-to-T rack Switch Delay
is the time delay from the track
command to the point when the output starts to change to ac-
quire a new signal level.
Pedestal Offset
is the offset voltage measured immediately af-
ter the AD9101 is switched from track to hold with the input
held at zero volts. It manifests itself as a dc offset during the
hold time.
Sampling Bandwidth
is the –3 dB frequency response from
the input to the hold capacitor under sampling conditions. It is
greater than the tracking bandwidth because it does not include
the bandwidth of the output amplifier which is optimized for
settling time rather than bandwidth.
T rack-to-Hold Settling T ime
is the time necessary for the
track to hold switching transient to settle to within 4 mV of its
final value.
T rack-to-Hold Switching T ransient
is the maximum peak
switch induced transient voltage which appears at the AD9101
output when it is switched from track to hold.
CLOCK
INPUTS
+2V
0V
-2V
ANALOG
INPUT (x 4)
+2V
0V
-2V
"1"
"0"
HOLD TO TRACK
SWITCH DELAY
TIME (1.5 ns)
APERTURE
DELAY
(–0.25 ns)
"TRACK"
ACQUISITION
TIME (SEE
TEXT)
VOLTAGE
LEVEL HELD
"HOLD"
SAMPLER OUTPUT SIGNAL (x 4)
AND AMPLIFIER OUTPUT SIGNAL
OBSERVED AT
HOLD CAPACITOR
OBSERVED AT
AMPLIFIER OUTPUT
"HOLD"
CLOCK
CLOCK
CLOCK
TRACK TO
HOLD
SETTLING
(4 ns)
Timing Diagram (500 ps/div)
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相關代理商/技術參數 |
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| AD9101AR | 制造商:Analog Devices 功能描述: |
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