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參數(shù)資料
| 型號： | AD9057BRSZ-RL40 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT 40MSPS 20-SSOP T/R |
| 標準包裝： | 1,500 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 40M |
| 數(shù)據接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 260mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 20-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
REV. D
–3–
AD9057
Test
AD9057BRS-40
AD9057BRS-60
AD9057BRS-80
Parameter
Temp
Level
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
DIGITAL OUTPUTS
Logic 1 Voltage (VDD = 3 V)
Full
VI
2.95
V
Logic 1 Voltage (VDD = 5 V)
Full
IV
4.95
V
Logic 0 Voltage
Full
VI
0.05
V
Output Coding
Offset Binary Code
POWER SUPPLY
VD Supply Current (VD = 5 V)
Full
VI
36
48
38
48
40
51
mA
VDD Supply Current (VDD = 3 V)
4
Full
VI
4.0
6.5
5.5
6.5
7.4
8.8
mA
Power Dissipation
5, 6
Full
VI
192
260
205
260
220
281
mW
Power-Down Dissipation
Full
VI
6
10
6
10
6
10
mW
Power Supply Rejection Ratio
(PSRR)
25
∞CV
333
mV/V
NOTES
1Gain error and gain temperature coefficient are based on the ADC only (with a fixed 2.5 V external reference).
2t
V and tPD are measured from the 1.5 V level of the encode to the 10%/90% levels of the digital output swing. The digital output load during test is not to exceed
an ac load of 10 pF or a dc current of
±40 mA.
3SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 1.0 V full-scale input range.
4Digital supply current based on V
DD = 3 V output drive with <10 pF loading under dynamic test conditions.
5Power dissipation is based on specified encode and 10.3 MHz analog input dynamic test conditions (V
D = 5 V
± 5%, VDD = 3 V ± 5%).
6Typical thermal impedance for the RS style (SSOP) 20-lead package :
qJC = 46∞C/W, qCA = 80∞C/W, and qJA = 126∞C/W.
Specifications subject to change without notice.
N
N + 3
N + 1
N + 2
N + 4
N + 5
AIN
ENCODE
DIGITAL
OUTPUTS
tA
tEH
tEL
tV
tPD
N – 3
N – 2
N – 1
N
N + 1
N + 2
APERTURE DELAY
PULSEWIDTH HIGH
PULSEWIDTH LOW
OUTPUT VALID TIME
OUTPUT PROP DELAY
tA
tEH
tEL
tV
tPD
4.0 ns
2.7 ns
6.6 ns
9.5 ns
166 ns
MIN
TYP
MAX
Figure 1. Timing Diagram
EXPLANATION OF TEST LEVELS
Test Level
Description
I
100% production tested.
II
100% production tested at 25
∞C and sample
tested at specified temperatures.
III
Sample tested only.
IV
Parameter is guaranteed by design and charac-
terization testing.
VParameter is a typical value only.
VI
100% production tested at 25
∞C; guaranteed
by design and characterization testing
for industrial temperature range.
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