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參數(shù)資料
| 型號(hào)： | AD872AJD |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 10MSPS 28-CDIP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 10M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 7 |
| 功率耗散（最大）： | 1.3W |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 28-CDIP（0.605"，15.37mm） |
| 供應(yīng)商設(shè)備封裝： | 28-CDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，雙極；1 個(gè)差分，雙極 |
REV. A
–14–
AD872A
ANALOG SUPPLIES AND GROUNDS
The AD872A features separate analog and digital supply and
ground pins, helping to minimize digital corruption of sensitive
analog signals. In general, AVSS and AVDD, the analog supplies,
should be decoupled to AGND, the analog common, as close to
the chip as physically possible. Care has been taken to minimize
the signal dependence of the power supply currents; however,
the analog supply currents will be proportional to the reference
input. With REFIN at 2.5 V, the typical current into AVDD is
85 mA, while the typical current out of AVSS is 115 mA. Typi-
cally, 30 mA will flow into the AGND pin.
Careful design and the use of differential circuitry provide the
AD872A with excellent rejection of power supply noise over a
wide range of frequencies, as illustrated in Figure 29.
FREQUENCY – Hz
SUPPLY
REJECTION
–
dB
–75
–80
–85
–90
–95
–100
AVSS
AVDD
DVDD
104
105
106
107
Figure 29. Power Supply Rejection vs. Frequency,
100 mV p-p Signal on Power Supplies
Figure 30 shows the degradation in SNR resulting from 100 mV
of power supply ripple at various frequencies. As Figure 30
shows, careful decoupling is required to realize the specified dy-
namic performance. Figure 34 demonstrates the recommended
decoupling strategy for the supply pins. Note that in extremely
noisy environments, a more elaborate supply filtering scheme
may be necessary.
FREQUENCY – Hz
SNR
–
dB
70
65
60
55
50
AVDD
AVSS
DVDD
104
105
106
107
Figure 30. SNR vs. Supply Noise Frequency
(fIN = 1 MHz)
DIGITAL SUPPLIES AND GROUNDS
The digital activity on the AD872A chip falls into two general
categories: CMOS correction logic, and CMOS output drivers.
The internal correction logic draws relatively small surges of
current, mainly during the clock transitions; in the 44-terminal
package, these currents flow through pins DGND and DVDD.
The output drivers draw large current impulses while the output
bits are changing. The size and duration of these currents are a
function of the load on the output bits: large capacitive loads are
to be avoided. In the 44-terminal package, the output drivers are
supplied through dedicated pins DRGND and DRVDD. Pin
count constraints in the 28-lead packages require that the digital
and driver supplies share package pins (although they have sepa-
rate bond wires and on-chip routing). The decoupling shown in
Figure 34 is appropriate for a reasonable capacitive load on the
digital outputs (typically 20 pF on each pin). Applications
involving greater digital loads should consider increasing the
digital decoupling proportionately, and/or using external buffers/
latches.
APPLICATIONS
OPTIONAL ZERO AND GAIN TRIM
The AD872A is factory trimmed to minimize zero error, gain
error and linearity errors. In some applications the zero and gain
errors of the AD872A need to be externally adjusted to zero. If
required, both zero error and gain error can be trimmed with ex-
ternal potentiometers as shown in Figure 31. Note that gain er-
ror adjustments must be made with an external reference.
Zero trim should be adjusted first. Connect VINA to ground and
adjust the 10 k
potentiometer such that a nominal digital out-
put code of 0000 0000 0000 (twos complement output) exists.
Note that the zero trim should be decoupled and that the accu-
racy of the
±2.5 V reference signals will directly affect the offset.
Gain error may then be calibrated by adjusting the REF IN
voltage. The REF IN voltage should be adjusted such that a
+1 V input on VINA results in the digital output code 01111
1111 1111 (twos complement output).
+2.5V
–2.5V
V INB
AD872A
0.1 F
10 F
10k
(a) ZERO TRIM
REF IN
AD872A
TRIM
V
OUT
REF43
(b) GAIN TRIM
100k
Figure 31. Zero and Gain Error Trims
DIGITAL OFFSET CORRECTION
The AD872A provides differential inputs that may be used to
correct any offset voltages on the analog input. For applications
where the input signal contains a dc offset, it may be advanta-
geous to apply a nulling voltage to the VINB input. Applying a
voltage equal to the dc offset will maximize the full-scale input
range and therefore the dynamic range. Offsets ranging from
–0.7 V to +0.5 V can be corrected.
OBSOLETE
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD872AJE | 制造商:Rochester Electronics LLC 功能描述:IC, 12-BIT 10 MSPS ADC - Bulk |
| AD872ASD | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 12-Bit 10 MSPS Monolithic A/D Converter |
| AD872ASD/883B | 制造商:Analog Devices 功能描述:ADC Single Pipelined 10Msps 12-bit Parallel 28-Pin CDIP 制造商:Analog Devices 功能描述:ADC SGL PIPELINED 10MSPS 12-BIT PARALLEL 28CDIP - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:IC, 12-BIT 10 MSPS ADC - Bulk 制造商:Analog Devices 功能描述:CONVERTER - ADC |
| AD872ASE | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 12-Bit 10 MSPS Monolithic A/D Converter |
| AD872ASE/883B | 制造商:Analog Devices 功能描述:ADC Single Pipelined 10Msps 12-bit Parallel 44-Pin LCC 制造商:Rochester Electronics LLC 功能描述:IC, 12-BIT 10 MSPS ADC - Bulk |
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