參數(shù)資料
型號: AD8607ARM-REEL
廠商: Analog Devices Inc
文件頁數(shù): 4/16頁
文件大?。?/td> 0K
描述: IC OPAMP GP R-R CMOS DUAL 8MSOP
標準包裝: 3,000
放大器類型: 通用
電路數(shù): 2
輸出類型: 滿擺幅
轉換速率: 0.1 V/µs
增益帶寬積: 400kHz
電流 - 輸入偏壓: 0.2pA
電壓 - 輸入偏移: 12µV
電流 - 電源: 40µA
電流 - 輸出 / 通道: 70mA
電壓 - 電源,單路/雙路(±): 1.8 V ~ 5 V,±0.9 V ~ 2.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應商設備封裝: 8-MSOP
包裝: 帶卷 (TR)
AD8603/AD8607/AD8609
Rev. C | Page 12 of 16
APPLICATIONS
NO PHASE REVERSAL
The AD8603/AD8607/AD8609 do not exhibit phase inversion
even when the input voltage exceeds the maximum input
common-mode voltage. Phase reversal can cause permanent
damage to the amplifier, resulting in system lockups. The
AD8603/AD8607/AD8609 can handle voltages of up to 1 V
over the supply.
V
O
LT
A
G
E
(
1V/
D
IV)
TIME (4s/DIV)
VS = ±2.5V
VIN = 6V p-p
AV = 1
RL = 10k
VIN
VOUT
04
35
6-
0
41
Figure 41. No Phase Response
INPUT OVERVOLTAGE PROTECTION
If a voltage 1 V higher than the supplies is applied at either
input, the use of a limiting series resistor is recommended. If
both inputs are used, each one should be protected with a
series resistor.
To ensure good protection, the current should be limited to a
maximum of 5 mA. The value of the limiting resistor can be
determined from the following equation:
(VIN VS)/(RS + 200 Ω) ≤ 5 mA
DRIVING CAPACITIVE LOADS
The AD8603/AD8607/AD8609 are capable of driving large
capacitive loads without oscillating. Figure 42 shows the output
of the AD8603/AD8607/AD8609 in response to a 100 mV input
signal, with a 2 nF capacitive load.
Although it is configured in positive unity gain (the worst case),
the AD8603 shows less than 20% overshoot. Simple additional
circuitry can eliminate ringing and overshoot.
One technique is the snubber network, which consists of a
series RC and a resistive load (see Figure 43). With the snubber
in place, the AD8603/AD8607/AD8609 are capable of driving
capacitive loads of 2 nF with no ringing and less than 3%
overshoot.
The use of the snubber circuit is usually recommended for unity
gain configurations. Higher gain configurations help improve
the stability of the circuit. Figure 44 shows the same output
response with the snubber in place.
VS = ±0.9V
VIN = 100mV
CL = 2nF
RL = 10k
0
43
56
-04
2
Figure 42. Output Response to a 2 nF Capacitive Load, Without Snubber
04
35
6-
04
3
CS
47pF
VCC
VEE
RS
150
200mV
CL
V+
V–
+
Figure 43. Snubber Network
VSY = ±0.9V
VIN = 100mV
CL = 2nF
RL = 10k
RS = 150
CS = 470pF
0
435
6-
0
44
Figure 44. Output Response to a 2 nF Capacitive Load with Snubber
Optimum values for RS and CS are determined empirically;
Table 5 lists a few starting values.
Table 5. Optimum Values for the Snubber Network
CL (pF)
RS (Ω)
CS (pF)
100 to ~500
500
680
1500
100
330
1600 to ~2000
400
100
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