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| 型號： | AD8429BRZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/20頁 |
| 文件大小： | 0K |
| 描述： | IC OP AMP INST LOW NOISE 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 放大器類型： | 儀表 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 22 V/µs |
| -3db帶寬： | 15MHz |
| 電流 - 輸入偏壓： | 150nA |
| 電壓 - 輸入偏移： | 50µV |
| 電流 - 電源： | 6.7mA |
| 電流 - 輸出 / 通道： | 35mA |
| 電壓 - 電源，單路/雙路(±)： | ±4 V ~ 18 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
AD8429
Rev. 0 | Page 15 of 20
THEORY OF OPERATION
A3
A1
A2
Q2
Q1
C1
C2
+IN
–IN
+VS
–VS
+VS
–VS
+VS
–VS
R3
5k
R4
5k
R5
5k
RG–
+VS
–VS
VOUT
REF
NODE 1
NODE 2
IB
COMPENSATION
IB
COMPENSATION
RG
VB
II
+VS
–VS
+VS
–VS
R6
5k
RG+
R2
3k
R1
3k
09
73
0-
0
58
Figure 46. Simplified Schematic
ARCHITECTURE
The AD8429 is based on the classic 3-op
-amp topology. This
topology has two stages: a preamplifier to provide differential
amplification followed by a difference amplifier that removes
the common-mode voltage and provides additional amplifica-
tion. Figure 46 shows a simplified schematic of the AD8429.
The first stage works as follows. To keep its two inputs matched,
Amplifier A1 must keep the collector of Q1 at a constant voltage.
It does this by forcing RG to be a precise diode drop from –IN.
Similarly, A2 forces RG+ to be a constant diode drop from +IN.
Therefore, a replica of the differential input voltage is placed
across the gain setting resistor, RG. The current that flows through
this resistance must also flow through the R1 and R2 resistors,
creating a gained differential signal between the A2 and A1
outputs.
The second stage is a G = 1 difference amplifier, composed of
Amplifier A3 and the R3 through R6 resistors. This stage removes
the common-mode signal from the amplified differential signal.
The transfer function of the AD8429 is
VOUT = G × (VIN+ VIN) + VREF
where:
G
R
G
kΩ
6
1+
=
GAIN SELECTION
Placing a resistor across the RG terminals sets the gain of the
AD8429, which can be calculated by referring to Table 5 or by
using the following gain equation:
1
kΩ
6
=
G
R
G
Table 5. Gains Achieved Using 1% Resistors
1% Standard Table Value of RG
Calculated Gain
6.04 kΩ
1.993
1.5 kΩ
5.000
665 Ω
10.02
316 Ω
19.99
121 Ω
50.59
60.4 Ω
100.3
30.1 Ω
200.3
12.1 Ω
496.9
6.04 Ω
994.4
3.01 Ω
1994
The AD8429 defaults to G = 1 when no gain resistor is used.
Add the tolerance and gain drift of the RG resistor to the
specifications of the AD8429 to determine the total gain accu-
racy of the system. When the gain resistor is not used, gain
error and gain drift are minimal.
RG Power Dissipation
The AD8429 duplicates the differential voltage across its inputs
onto the RG resistor. Choose an RG resistor size sufficient to
handle the expected power dissipation.
REFERENCE TERMINAL
The output voltage of the AD8429 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal must be offset to a precise midsupply level. For
example, a voltage source can be tied to the REF pin to level
shift the output, allowing the AD8429 to drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +VS or VS by more than 0.3 V.
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