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參數(shù)資料
| 型號： | AD841SQ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP GP 40MHZ 50MA 14CDIP |
| 標準包裝： | 25 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 300 V/µs |
| 增益帶寬積： | 40MHz |
| 電流 - 輸入偏壓： | 3.5µA |
| 電壓 - 輸入偏移： | 500µV |
| 電流 - 電源： | 11mA |
| 電流 - 輸出 / 通道： | 50mA |
| 電壓 - 電源，單路/雙路(±)： | ±5 V ~ 18 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 14-CDIP（0.300"，7.62mm） |
| 供應商設備封裝： | 14-CERDIP |
| 包裝： | 管件 |
AD841
Data Sheet
Rev. C | Page 10 of 16
THEORY OF OPERATION
OFFSET NULLING
The input offset voltage of the AD841 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 28 can be used.
Figure 28. Offset Nulling (PDIP Pinout)
INPUT CONSIDERATIONS
where the input to the AD841 is subjected to transient or
continuous overload voltages exceeding the ±6 V maximum
differential limit. This resistor provides protection for the input
transistors by limiting the maximum current that can be forced
into the input.
For high performance circuits it is recommended that a resistor
errors by matching the impedance at each input. The output
voltage error caused by the offset current is more than an order
of magnitude less than the error present if the bias current error
is not removed.
AD841 SETTLING TIME
Figure 29 and Figure 31 show the settling performance of the
AD841 in the test circuit shown in Figure 30.
Settling time is defined as the interval of time from the
application of an ideal step function input until the closed-loop
amplifier output has entered and remains within a specified
error band.
This definition encompasses the major components, which
comprise settling time. They include
Propagation delay through the amplifier
Slewing time to approach the final output value
The time of recovery from the overload associated
with slewing
Linear settling to within the specified error band
Expressed in these terms, the measurement of settling time
is obviously a challenge and needs to be done accurately to
assure the user that the amplifier is worth consideration for
the application.
Figure 29. AD841 0.01% Settling Time
Figure 30. Settling Time Test Circuit
Measurement of the 0.01% settling in 110 ns was accomplished
by amplifying the error signal from a false summing junction
with a very high speed proprietary hybrid error amplifier
specially designed to enable testing of small settling errors.
The device under test was driving a 500 Ω load. The input to
the error amp is clamped to avoid possible problems associated
with the overdrive recovery of the oscilloscope input amplifier.
The error amp gains the error from the false summing junction
by 10, and it contains a gain vernier to fine trim the gain.
11
12
3
4
5
10
–
+
AD841
+VS
6
–VS
2.2F
0.1F
RL
INPUT
OUTPUT
100
1
1340-
028
100
90
10
0%
10mV
5V
20ns
OUTPUT ERROR:
0.02%/DIV
OUTPUT:
5V/DIV
1
1340-
029
DDD5109
FLAT-TOP
PULSE
GENERATOR
11
6
4
5
10
–
+
AD841
+15V
–15V
2.2F
0.1F
2.2F
0.1F
499
50
499
1k
ERROR
AMP
(×10)
TEK
7A13
T
EK
7603
OS
C
ILLOS
C
OP
E
TEK
7A18
HP6263
FET PROBE
TEK P6201
1
1340-
030
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD841SQ/883B | 功能描述:高速運算放大器 FAST SETTLING H.S. OP AMP RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 電壓增益 dB:116 dB 輸入補償電壓:0.5 mV 轉(zhuǎn)換速度:55 V/us 工作電源電壓:36 V 電源電流:7.5 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube 產(chǎn)品: |
| AD842 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Wideband, High Output Current, Fast Settling Op Amp |
| AD8420 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Noise, Low Gain Drift, G = 2000 |
| AD8420_12 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Wide Supply Range, Micropower, |
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