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參數(shù)資料
| 型號(hào)： | AD8343ARUZ-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 混頻器 |
| 英文描述： | 0 MHz - 2500 MHz RF/MICROWAVE DOUBLE BALANCED MIXER |
| 封裝： | LEAD FREE, PLASTIC, TSSOP-14 |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 2171K |
| 代理商： | AD8343ARUZ-REEL7 |
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AD8343
Rev. B | Page 22 of 32
For the device input, capacitive common-mode loading tends to
produce an unstable circuit, particularly at low frequencies (see
Figure 61). Fortunately, either type of single-ended-to-differential
conversion (transmission line balun or flux-coupled transformer)
tends to produce inductive loading, although some matching
network topologies and/or component values circumvent this
desirable behavior. In general, a simulation of the common-
mode termination seen by the AD8343’s input port is plotted
against the input stability circles to check stability. This is
especially recommended if the single-ended-to-differential
conversion is done with a discrete component circuit.
LOCAL OSCILLATOR INPUT INTERFACE
(LOIP, LOIM)
The LO terminals of the AD8343 are internally biased;
connections to these terminals should include dc blocks,
except as noted below in the DC Coupling the LO section.
The differential LO input return loss (with a 50 Ω differential
input impedance) is presented in Figure 64. As shown, this port
has a typical differential return loss of better than 9.5 dB (2:1 V
SWR). If better return loss is desired for this port, differential
matching techniques can also be applied.
–25
0
–5
–10
–30
–15
–20
0
500
1000
1500
2000
2500
01
03
4-
06
4
R
E
F
L
EC
T
IO
N
C
O
EF
F
IC
IEN
T
(d
B
)
FREQUENCY (50MHz TO 2500MHz)
Figure 64. LO Input Differential Reflection Coefficient
At low LO frequencies, it is reasonable to drive the AD8343
with a single-ended LO, connecting the undriven LO pin to
GND through a dc block. This results in an LO input imped-
ance closer to 25 Ω at low frequencies, which should be factored
into the design. At higher LO frequencies, differential drive is
strongly recommended.
The suggested minimum LO power level is about –12 dBm.
This can be seen in Figure 65.
5
0
1
2
3
4
25
0
5
10
15
20
–40
–30
–20
–10
01
034
-06
5
CO
NV
E
RS
IO
N
G
AI
N
(
d
B)
NO
IS
E
F
IG
URE
(d
B
)
LO POWER (dBm)
NOISE FIGURE
CONVERSION GAIN
INPUT RF = 900MHz
OUTPUT IF = 170MHz
LO LOW SIDE INJECTION
Figure 65. Gain and Noise Figure vs. LO Input Power
DC COUPLING THE LO
The AD8343’s LO limiting amplifier chain is internally
dc-coupled. In some applications or experimental situations,
it is useful to exploit this property. Following is the recom-
mended way to do so.
The LO pins are internally biased at about 360 mV with respect
to COMM. Driving the LO to either extreme requires injecting
several hundred microamps into one LO pin and extracting
about the same amount of current from the other. The incre-
mental impedance at each pin is about 25 Ω, so the voltage level
on each pin is disturbed very little by the application of external
currents in that range.
Figure 66 illustrates how to drive the LO port with continuous
dc and also from standard ECL powered by –5.2 V.
13k
1k
BIAS
AD8343
VPOS
DCPL
PWDN
LOIP
LOIM
INPP
INPM
OU
T
P
OU
TM
COMM
LO
DRIVER
4
6
10
9
2
3
12
13
14
11
8
7
1
5
3.6k
1.2k
390
1.2k
BIAS
AD8343
VPOS
DCPL
PWDN
LOIP
LOIM
INPP
INPM
OU
TP
OU
TM
COMM
LO
DRIVER
4
6
10
9
2
3
12
13
14
11
8
7
1
5
01
03
4-
0
66
–5.2V
+5V
ECL
–5.2V
E
CL
CO
NT
INUO
US
DC
Figure 66. DC Interfaces to the LO Port
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