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| 型號(hào)： | AD8324ACP-EVAL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 3.3 V Upstream Cable Line Driver |
| 中文描述： | 3.3伏上行電纜線路驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 11/16頁(yè) |
| 文件大?。?/td> | 516K |
| 代理商： | AD8324ACP-EVAL |
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AD8324
Rev. 0 | Page 11 of 16
CLK
SDATA
DATEN
TXEN
GND
V
CC
GND
GND
V
IN+
V
IN–
V
CC
Z
IN
= 150
V
CC
TXEN
RAMP
V
OUT+
V
OUT–
GND
DATEN
SDATA
CLK
GND
BYP
SLEEP
GND
NC
AD8324-JRQ
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1k
174
1k
1k
1k
1k
SLEEP
TO DIPLEXER
Z
IN
= 75
TOKO 458PT-1556
V
IN+
V
IN–
10
μ
F
0.1
μ
F
0.1
μ
F
1:1
0.1
μ
F
0.1
μ
F
0
Figure 23. Typical Application Circuit
Table 6. Adjacent Channel Power
Channel Symbol Rate (kSym/s)
160
320
640
1280
2560
5120
POWER SUPPLY
The 3.3 V supply should be delivered to each of the V
CC
pins via
a low impedance power bus. This ensures that each pin is at the
same potential. The power bus should be decoupled to ground
using a 10 μF tantalum capacitor located close to the AD8324.
In addition to the 10 μF capacitor, V
CC
pins should be decoupled
to ground with ceramic chip capacitors located close to the pins.
The bypass pin, labeled BYP, should also be decoupled. The PCB
should have a low impedance ground plane covering all unused
portions of the board, except in areas of the board where input
and output traces are in close proximity to the AD8324 and the
output transformer. All AD8324 ground pins must be connected
to the ground plane to ensure proper grounding of all internal
nodes.
Adjacent Channel Symbol Rate (kSym/s)
640
1280
–68
–71
–66
–70
–65
–67
–65
–66
–66
–66
–67
–67
160
–63
–63
–64
–67
–70
–72
320
–64
–64
–64
–65
–67
–70
2560
–72
–72
–71
–68
–67
–64
5120
–66
–67
–67
–67
–65
–64
SIGNAL INTEGRITY LAYOUT CONSIDERATIONS
Careful attention to printed circuit board layout details will
prevent problems due to board parasitics. Proper RF design
techniques are mandatory. The differential input and output
traces should be kept as short as possible. Keeping the traces
short will minimize parasitic capacitance and inductance, which
is most critical between the outputs of the AD8324 and the 1:1
output transformer. It is also critical that all differential signal
paths be symmetrical in length and width. In addition, the input
and output traces should be adequately spaced to minimize
coupling (crosstalk) through the board. Following these guide-
lines will optimize the overall performance of the AD8324 in all
applications.
INITIAL POWER-UP
When the supply voltage is first applied to the AD8324, the gain
of the amplifier is initially set to gain code 1. As power is first
applied to the amplifier, the TXEN pin should be held low
(Logic 0) to prevent forward signal transmission. After power
has been applied to the amplifier, the gain can be set to the
desired level by following the procedure provided in the Gain
Programming for the AD8324 section. The TXEN pin can then
be brought from Logic 0 to Logic 1, enabling forward signal
transmission at the desired gain level.
RAMP PIN AND BYP PIN FEATURES
The RAMP pin (Pin 15) is used to control the length of the
burst on and off transients. By default, leaving the RAMP pin
unconnected will result in a transient that is fully compliant
with DOCSIS 2.0 Section 6.2.21.2, Spurious Emissions During
Burst On/Off Transients. DOCSIS requires that all between
burst transients must be dissipated no faster than 2 μs. Adding
capacitance to the RAMP pin will slow the dissipation even
more.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD8324ACP-REEL7 | 3.3 V Upstream Cable Line Driver |
| AD8324JRQ | 3.3 V Upstream Cable Line Driver |
| AD8324JRQ-EVAL | 3.3 V Upstream Cable Line Driver |
| AD8324JRQ-REEL | 3.3 V Upstream Cable Line Driver |
| AD8324JRQ-REEL7 | 3.3 V Upstream Cable Line Driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8324ACP-R2 | 制造商:Analog Devices 功能描述:+3.3 V UPSTREAM CABLE LINE DRIVER - Tape and Reel |
| AD8324ACP-REEL7 | 制造商:Analog Devices 功能描述:SP Amp Line Driver Amp Single 3.47V 20-Pin LFCSP EP T/R |
| AD8324ACPZ | 功能描述:IC LINE DRIVER CATV 3.3V 20LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:電平移位器 應(yīng)用:LCD 電視機(jī)/監(jiān)控器 安裝類型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:28-WQFN（4x4）裸露焊盤 包裝:帶卷 (TR) 其它名稱:296-32523-2TPS65198RUYT-ND |
| AD8324ACPZ-REEL7 | 功能描述:IC LINE DRIVER CATV 3.3V 20LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動(dòng)電話，手機(jī)，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| AD8324JRQ | 制造商:Analog Devices 功能描述:SP Amp Line Driver Amp Single 3.47V 20-Pin QSOP Tube 制造商:Rochester Electronics LLC 功能描述:LOW COST 3.3V CABLE LINE DRIVER - Bulk 制造商:Analog Devices 功能描述:CABLE LINE DRIVER 3.3V SMD 8324 |
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