參數(shù)資料
型號: AD8315ACP-REEL7
廠商: ANALOG DEVICES INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: 50 dB GSM PA Controller
中文描述: SPECIALTY TELECOM CIRCUIT, DSO8
封裝: 2 X 3 MM, LFCSP-8
文件頁數(shù): 2/20頁
文件大小: 1787K
代理商: AD8315ACP-REEL7
REV. B
–2–
AD8315–SPECIFICATIONS
(V
S
= 2.7 V, T = 25 C, 52.3 termination on RFIN, unless otherwise noted.)
Parameter
Conditions
Min
Typ
Max
Unit
OVERALL FUNCTION
Frequency Range
1
Input Voltage Range
Equivalent dBm Range
Logarithmic Slope
2
Logarithmic Intercept
2
Equivalent dBm Level
To Meet All Specifications
±
1 dB Log Conformance, 0.1 GHz
0.1
–57
–44
21.5
–79
–66
2.5
–11
+2
25.5
–64
–51
GHz
dBV
dBm
mV/dB
dBV
dBm
0.1 GHz
0.1 GHz
24
–70
–57
RF INPUT INTERFACE
Input Resistance
3
Input Capacitance
3
Pin RFIN
0.1 GHz
0.1 GHz
2.8
0.9
k
W
pF
OUTPUT
Minimum Output Voltage
Pin VAPC
VSET
200 mV, ENBL High
ENBL Low
R
L
800
W
85
C, V
POS
= 3 V, I
OUT
= 6 mA
2.7 V
VPOS
5.5 V, R
L
=
Source/Sink
0.25
0.27
0.02
0.3
V
V
V
V
V
mA/
m
A
nV
÷
Hz
nV/
÷
Hz
Maximum Output Voltage
vs. Temperature
4
General Limit
Output Current Drive
Output Buffer Noise
Output Noise
2.45
2.54
2.6
VPOS – 0.1
5/200
25
130
RF Input = 2 GHz, 0 dBm, f
NOISE
= 100 kHz,
C
FLT
= 220 pF
0.2 V to 2.6 V Swing
10%–90%, 1.2 V Step (V
SET
), Open Loop
5
FLTR = Open, Refer to TPC 24
Small Signal Bandwidth
Slew Rate
Response Time
30
13
150
MHz
V/
m
s
ns
SETPOINT INTERFACE
Nominal Input Range
Logarithmic Scale Factor
Input Resistance
Slew Rate
Pin VSET
Corresponding to Central 50 dB
0.25
1.4
V
dB/V
k
W
V/
m
s
43.5
100
16
ENABLE INTERFACE
Logic Level to Enable Power
Input Current when Enable High
Logic Level to Disable Power
Enable Time
Pin ENBL
1.8
V
POS
V
m
A
V
m
s
20
0.8
5
Time from ENBL High to V
APC
within 1% of
Final Value, V
SET
200 mV, Refer to TPC 21
Time from ENBL Low to V
APC
within 1% of
Final Value, V
SET
200 mV, Refer to TPC 21
Time from VPOS/ENBL High to V
APC
within
1% of Final Value, V
SET
200 mV, Refer to
TPC 26
Time from VPOS/ENBL Low to V
APC
within
1% of Final Value, V
SET
200 mV, Refer to
TPC 26
4
Disable Time
8
9
m
s
Power-On/Enable Time
2
3
m
s
100
200
ns
POWER INTERFACE
Supply Voltage
Quiescent Current
Over Temperature
Disable Current
6
Over Temperature
Pin VPOS
2.7
5.5
10.7
12.9
10
13
V
mA
mA
m
A
m
A
ENBL High
–30
C
T
A
+85
C
ENBL Low
–30
C
T
A
+85
C
8.5
4
NOTES
1
Operation down to 0.02 GHz is possible.
2
Mean and Standard Deviation specifications are available in Table I.
3
See TPC 9 for plot of Input Impedance vs. Frequency.
4
This parameter is guaranteed but not tested in production. Limit is –3 sigma from the mean.
5
Response time in a closed-loop system will depend upon the filter capacitor (C
) used and the response of the variable gain element.
6
This parameter is guaranteed but not tested in production. Maximum specified limit on this parameter is the +6 sigma value.
Specifications subject to change without notice.
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