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參數(shù)資料
| 型號： | AD8310ARM-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Fast, Voltage-Out DC-440 MHz 95 dB Logarithmic Amplifier |
| 中文描述： | LOG OR ANTILOG AMPLIFIER, 440 MHz BAND WIDTH, PDSO8 |
| 封裝： | MO-187AA, MSOP-8 |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 323K |
| 代理商： | AD8310ARM-REEL |
AD8310
–15–
REV. A
5V
0.01
m
F
SIGNAL
INPUT
AD8138
0.1
m
F
5V
499
V
499
V
499
V
499
V
10k
V
0.1
m
F
5V
10k
V
NC
6
INHI ENBL
BFIN VPOS
INLO COMM OFLT VOUT
1
2
AD8310
V
OUT
3
4
8
7
5
5V
3.01k
V
1.87k
V
50
V
2.5V
NC = NO CONNECT
Figure 36. DC-Coupled Log Amp
It is necessary in this application to trim the offset voltage of
the AD8138. The internal offset compensation circuitry of the
AD8310 is disabled by applying a nominal voltage of around
1.9 V to the OFLF pin. So the trim on the AD8138 is effectively
trimming both devices’ offsets. The trim is done by grounding
the circuit’s input and slightly varying the gain resistors on the
AD8138’s inverting input (a 50
potentiometer is used in this
example) until the voltage on the AD8310’s output reaches a
minimum.
After trimming, the lower end of the dynamic range is limited
by the broadband noise at the output of the AD8138, which
is approximately 425
μ
V p-p. A differential low-pass filter may
be added between the AD8138 and the AD8310 when the very
fast pulse response of the circuit is not required.
INPUT LEVEL – mV
0.1
R
1
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
10
100
1000
2.3
2.5
2.7
Figure 37. Transfer Function of DC-Coupled Log Amp
Application
Evaluation Board
An evaluation board, carefully laid out and tested to demon-
strate the specified high-speed performance of the AD8310 is
available. Figure 38 shows the schematic of the evaluation board,
which fairly closely follows the basic connections schematic
shown in Figure 25. Connectors INHI, INLO and VOUT are
SMA type; supply and ground are connected to vector pins TP1
and TP1, switches and component settings for different setups
are described in Table III. The layout and silkscreen for the
component side of the board are shown in Figure 39 and Figure
40. For ordering information, please refer to the Ordering Guide.
C2
0.01
m
F
INHI ENBL
BFIN VPOS
INLO COMM OFLT VOUT
1
2
AD8310
3
4
8
7
6
5
C4
0.01
m
F
C1
0.01
m
F
R3
52.3
V
R4
0
V
R1
0
V
INHI
INLO
TP2
C7
(OPEN)
(0603 PAD)
W1
W2
C6
(OPEN)
(0603 PAD)
R7
(OPEN)
(0603 PAD)
R6
0
V
V
OUT
C5
(OPEN, 0805 PAD)
C3
(OPEN)
(0603
PAD)
SW1
A
B
R5
0
V
TP1
V
S
Figure 38. Evaluation Board Schematic
Figure 39. Layout of Component Side of Evaluation Board
Figure 40. Component Side Silkscreen of Evaluation
Board
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