參數(shù)資料
型號： AD8300ARZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 3/8頁
文件大?。?/td> 0K
描述： IC DAC 12BIT SERIAL 8SOIC
產(chǎn)品培訓模塊： Data Converter Fundamentals
DAC Architectures
標準包裝： 2,500
設置時間： 14µs
位數(shù)： 12
數(shù)據(jù)接口： 串行
轉換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 5.1mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應商設備封裝： 8-SOIC
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 1 電壓，單極
采樣率（每秒）： 71k
REV. A
–3–
AD8300
+5 V OPERATION
Parameter
Symbol
Condition
Min
Typ
Max
Units
STATIC PERFORMANCE
Resolution
N
[Note 1]
12
Bits
Relative Accuracy
INL
–2
±1/2
+2
LSB
Differential Nonlinearity
2
DNL
Monotonic
–1
±1/2
+1
LSB
Zero-Scale Error
VZSE
Data = 000H
+1/2
+3
mV
Full-Scale Voltage
3
VFS
Data = FFFH
2.039 2.0475 2.056
Volts
Full-Scale Tempco
TCVFS
[Notes 3, 4]
16
ppm/
°C
ANALOG OUTPUT
Output Current (Source)
IOUT
Data = 800H,
V
OUT = 5 LSB
5
mA
Output Current (Sink)
IOUT
Data = 800H, VOUT = 5 LSB
2
mA
Load Regulation
LREG
RL = 200
to ∞, Data = 800
H
1.5
5
LSB
Output Resistance to GND
ROUT
Data = 000H
30
Capacitive Load
CL
No Oscillation4
500
pF
LOGIC INPUTS
Logic Input Low Voltage
VIL
0.8
V
Logic Input High Voltage
VIH
2.4
V
Input Leakage Current
IIL
10
A
Input Capacitance
CIL
10
pF
INTERFACE TIMING
SPECIFICATIONS
4, 5
Clock Width High
tCH
30
ns
Clock Width Low
tCL
30
ns
Load Pulsewidth
tLDW
30
ns
Data Setup
tDS
15
ns
Data Hold
tDH
15
ns
Clear Pulsewidth
tCLWR
30
ns
Load Setup
tLD1
15
ns
Load Hold
tLD2
30
ns
Select
tCSS
30
ns
Deselect
tCSH
30
ns
AC CHARACTERISTICS
4
Voltage Output Settling Time
tS
To
±0.2% of Full Scale
6
s
To
±1 LSB of Final Value6
13
s
Output Slew Rate
SR
Data = 000H to FFFH to 000H
2.2
V/
s
DAC Glitch
15
nV/s
Digital Feedthrough
15
nV/s
SUPPLY CHARACTERISTICS
Power Supply Range
VDD RANGE
DNL <
±1 LSB
2.7
5.5
V
Positive Supply Current
IDD
VDD = 5 V, VIL = 0 V, Data = 000H
1.2
1.7
mA
VDD = 5.5 V, VIH = 2.3 V, Data = FFFH
2.8
4.0
mA
Power Dissipation
PDISS
VDD = 5 V, VIL = 0 V, Data = 000H
6
5.1
mW
Power Supply Sensitivity
PSS
V
DD =
±10%
0.001
0.006
%/%
NOTES
11 LSB = 0.5 mV for 0 V to +2.0475 V output range.
2The first two codes (000
H, 001H) are excluded from the linearity error measurement.
3Includes internal voltage reference error.
4These parameters are guaranteed by design and not subject to production testing.
5All input control signals are specified with t
R = tF = 2 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
6The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in
this 6 LSB region.
Specifications subject to change without notice.
(@ VDD = +5 V
10%, –40 C
≤ T
A
≤ +85 C, unless otherwise noted)
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