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參數(shù)資料
| 型號： | AD8300AN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | +3 Volt, Serial Input Complete 12-Bit DAC |
| 中文描述： | SERIAL INPUT LOADING, 14 us SETTLING TIME, 12-BIT DAC, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁數(shù)： | 8/8頁 |
| 文件大?。?/td> | 245K |
| 代理商： | AD8300AN |
REV. A
AD8300
–8–
C
P
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead SOIC (SO-8)
8
5
4
1
0.1968 (5.00)
0.1890 (4.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0500 (1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
8
0
8
0.0196 (0.50)
0.0099 (0.25)
3
45
8
8-Lead Plastic DIP (N-8)
SEATING
PLANE
0.015
(0.381)
TYP
0.210
(5.33)
MAX
0.022 (0.558)
0.014 (0.356)
0.160 (4.06)
0.115 (2.93)
0.070 (1.77)
0.045 (1.15)
0.130
(3.30)
MIN
8
1
4
5
PIN 1
0.280 (7.11)
0.240 (6.10)
0.100 (2.54)
BSC
0.430 (10.92)
0.348 (8.84)
0.195 (4.95)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
0.325 (8.25)
0.300 (7.62)
15
8
0
8
V
OH
and V
OL
voltage levels. Consequently, for optimum dissipa-
tion use of CMOS logic versus TTL provides minimal dissipa-
tion in the static state. A V
INL
= 0 V on the logic input pins
provides the lowest standby dissipation of 1.2 mA with a +3.3 V
power supply.
As with any analog system, it is recommended that the AD8300
power supply be bypassed on the same PC card that contains
the chip. Figure 8 shows the power supply rejection versus fre-
quency performance. This should be taken into account when
using higher frequency switched-mode power supplies with
ripple frequencies of 100 kHz and higher.
One advantage of the rail-to-rail output amplifiers used in the
AD8300 is the wide range of usable supply voltage. The part is
fully specified and tested over temperature for operation from
+2.7 V to +5.5 V. If reduced linearity and source current capa-
bility near full scale can be tolerated, operation of the AD8300
is possible down to +2.1 volts. The minimum operating supply
voltage versus load current plot in Figure 2 provides information
for operation below V
DD
= +2.7 V.
TIMING AND CONTROL
The AD8300 has a separate serial-input register from the 12-bit
DAC register that allows preloading of a new data value MSB
first into the serial register without disturbing the present DAC
output voltage value. Data can only be loaded when the
CS
pin
is active low. After the new value is fully loaded in the serial-
input register, it can be asynchronously transferred to the DAC
register by strobing the
LD
pin. The DAC register uses a level
sensitive
LD
strobe that should be returned high before any new
data is loaded into the serial-input register. At any time the
contents of the DAC resister can be reset to zero by strobing the
CLR
pin which causes the DAC output voltage to go to zero
volts. All of the timing requirements are detailed in Figure 3
along with Table I. Control Logic Truth Table.
All digital inputs are protected with a Zener type ESD protection
structure (Figure 22) that allows logic input voltages to exceed
the V
DD
supply voltage. This feature can be useful if the user is
loading one or more of the digital inputs with a 5 V CMOS logic
input voltage level while operating the AD8300 on a +3.3 V
power supply. If this mode of interface is used, make sure that
the V
OL
of the +5 V CMOS meets the V
IL
input requirement of
the AD8300 operating at 3 V. See Figure 5 for the effect on
digital logic input threshold versus operating V
DD
supply voltage.
V
DD
LOGIC
IN
GND
Figure 22. Equivalent Digital Input ESD Protection
Unipolar Output Operation
This is the basic mode of operation for the AD8300. The
AD8300 has been designed to drive loads as low as 400
in
parallel with 500 pF. The code table for this operation is shown
in Table II.
APPLICATIONS INFORMATION
See DAC8512 data sheet for additional application circuit ideas.
Table II. Unipolar Code Table
Hexadecimal
Number in
DAC Register
Decimal
Number in
DAC Register
Analog Output
Voltage (V)
FFF
801
800
7FF
000
4095
2049
2048
2047
0
+2.0475
+1.0245
+1.0240
+1.0235
+0.0000
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