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| 型號： | AD8226ARMZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP INST R-R LP 13MA 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 放大器類型： | 儀表 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 0.6 V/µs |
| -3db帶寬： | 1.5MHz |
| 電流 - 輸入偏壓： | 20nA |
| 電壓 - 輸入偏移： | 200µV |
| 電流 - 電源： | 350µA |
| 電流 - 輸出 / 通道： | 13mA |
| 電壓 - 電源，單路/雙路(±)： | 2.2 V ~ 36 V，±1.35 V ~ 18 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
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AD8226
Data Sheet
Rev. C | Page 20 of 28
REFERENCE TERMINAL
The output voltage of the AD8226 is developed with respect to
the potential on the reference terminal. This is useful when the
output signal needs to be offset to a precise midsupply level. For
example, a voltage source can be tied to the REF pin to level-
shift the output so that the AD8226 can drive a single-supply
ADC. The REF pin is protected with ESD diodes and should
not exceed either +VS or VS by more than 0.3 V.
For the best performance, source impedance to the REF
terminal should be kept below 2 . As shown in Figure 58,
the reference terminal, REF, is at one end of a 50 kΩ resistor.
Additional impedance at the REF terminal adds to this 50 kΩ
resistor and results in amplification of the signal connected to
the positive input. The amplification from the additional RREF
can be computed by 2(50 kΩ + RREF)/(100 kΩ + RREF).
Only the positive signal path is amplified; the negative path
is unaffected. This uneven amplification degrades CMRR.
INCORRECT
V
CORRECT
AD8226
OP1177
+
–
V
07036-
004
REF
AD8226
REF
Figure 59. Driving the Reference Pin
INPUT VOLTAGE RANGE
Figure 9 through Figure 15 and Figure 18 show the allowable
common-mode input voltage ranges for various output voltages
and supply voltages. The 3-op-amp architecture of the AD8226
applies gain in the first stage before removing common-mode
voltage with the difference amplifier stage. Internal nodes between
the first and second stages (Node 1 and Node 2 in Figure 58)
experience a combination of a gained signal, a common-mode
signal, and a diode drop. This combined signal can be limited
by the voltage supplies even when the individual input and
output signals are not limited.
For most applications, Figure 9 through Figure 15 and Figure 18
provide sufficient information to achieve a good design. For
applications where a more detailed understanding is needed,
Equation 1 to Equation 3 can be used to understand how the
gain (G), common-mode input voltage (VCM), differential input
voltage (VDIFF), and reference voltage (VREF) interact. The values for
These three formulas, along with the input and output range
specifications in Table 2 and Table 3, set the operating boundaries
of the part.
LIMIT
S
DIFF
CM
V
G
V
+
>
2
)
)(
(
(1)
LIMIT
S
DIFF
CM
V
G
V
+
+
<
+
2
)
)(
(
(2)
LIMIT
REF
S
REF
CM
DIFF
V
G
V
_
2
)
)(
(
+
<
+
(3)
Table 8. Input Voltage Range Constants for Various
Temperatures
Temperature
V
LIMIT
V
+LIMIT
V
REF_LIMIT
40°C
0.55 V
0.8 V
1.3 V
+25°C
0.35 V
0.7 V
1.15 V
+85°C
0.15 V
0.65 V
1.05 V
+125°C
0.05 V
0.6 V
0.9 V
Performance Across Temperature
The common-mode input range shifts upward with temper-
ature. At cold temperatures, the part requires extra headroom
from the positive supply, and operation near the negative supply
has more margin. Conversely, hot temperatures require less
headroom from the positive supply, but are the worst-case
conditions for input voltages near the negative supply.
Recommendation for Best Performance
A typical part functions up to the boundaries described in this
section. However, for best performance, designing with a few
hundred millivolts extra margin is recommended. As signals
approach the boundary, internal transistors begin to saturate,
which can affect frequency and linearity performance.
If the application requirements exceed the boundaries, one
solution is to apply less gain with the AD8226, and then apply
additional gain later in the signal chain. Another option is to
use the pin-compatible AD8227.
LAYOUT
To ensure optimum performance of the AD8226 at the PCB
level, care must be taken in the design of the board layout.
The AD8226 pins are arranged in a logical manner to aid in
this task.
8
7
6
5
1
2
3
4
–IN
RG
+VS
VOUT
REF
–VS
+IN
TOP VIEW
(Not to Scale)
AD8226
07036-
005
Figure 60. Pinout Diagram
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