參數(shù)資料
型號(hào)： AD8196ACPZ-RL
廠商： ANALOG DEVICES INC
元件分類： 運(yùn)動(dòng)控制電子
英文描述： 2:1 HDMI/DVI Switch with Equalization
中文描述： 2-CHANNEL, AUDIO/VIDEO SWITCH, PQCC56
封裝： 8 X 8 MM, LEAD FREE, PLASTIC, MO-220VLLD-2, LFCSP-56
文件頁(yè)數(shù)： 20/24頁(yè)
文件大?。?/td> 388K
代理商： AD8196ACPZ-RL
AD8196
Preliminary Technical Data
Layout for the TMDS Signals
The TMDS differential pairs can either be microstrip traces,
routed on the outer layer of a board, or stripline traces, routed
on an internal layer of the board. If microstrip traces are used,
there should be a continuous reference plane on the PCB layer
directly below the traces. If stripline traces are used, they must
be sandwiched between two continuous reference planes in the
PCB stack-up. Additionally, the p and n of each differential pair
must have a controlled differential impedance of 100 Ω. The
characteristic impedance of a differential pair is a function of
several variables including the trace width, the distance separating
the two traces, the spacing between the traces and the reference
plane, and the dielectric constant of the PC board binder material.
Interlayer vias introduce impedance discontinuities that can
cause reflections and jitter on the signal path, therefore, it is
preferable to route the TMDS lines exclusively on one layer of the
board, particularly for the input traces. Additionally, to prevent
unwanted signal coupling and interference, route the TMDS
signals away from other signals and noise sources on the PCB.
PrA | Page 20 of 24
Both traces of a given differential pair must be equal in length
to minimize intrapair skew. Maintaining the physical symmetry
of a differential pair is integral to ensuring its signal integrity;
excessive intrapair skew can introduce jitter through duty cycle
distortion (DCD). The p and n of a given differential pair should
always be routed together in order to establish the required 100 Ω
differential impedance. Enough space should be left between
the differential pairs of a given group so that the n of one pair
does not couple to the p of another pair. For example, one tech-
nique is to make the interpair distance 4 to 10 times wider than
the intrapair spacing.
Any one group of four TMDS channels (Input A, Input B, or the
output) should have closely matched trace lengths in order to
minimize interpair skew. Severe interpair skew can cause the
data on the four different channels of a group to arrive out of
alignment with one another. A good practice is to match the
trace lengths for a given group of four channels to within
0.05 inches on FR4 material.
Minimizing intra- and interpair skew becomes increasingly
important as data rates increase. Any introduced error will
constitute a correspondingly larger fraction of a bit period at
higher data rates.
While the AD8196 features input equalization and output pre-
emphasis, the length of the TMDS traces should be minimized
to reduce overall system signal degradation. Commonly used
PC board material such as FR4 is lossy at high frequencies, so
long traces on the circuit board increase signal attenuation,
resulting in decreased signal swing and increased jitter through
intersymbol interference (ISI).
Controlling the Characteristic Impedance of a TMDS
Differential Pair
The characteristic impedance of a differential pair depends on a
number of variables including the trace width, the distance
between the two traces, the height of the dielectric material
between the trace and the reference plane below it, and the
dielectric constant of the PCB binder material. To a lesser
extent, the characteristic impedance also depends upon the
trace thickness and the presence of solder mask. There are
many combinations that can produce the correct characteristic
impedance. It is generally required to work with the PC board
fabricator to obtain a set of parameters to produce the desired
results.
One consideration is how to guarantee a differential pair with a
differential impedance of 100 Ω over the entire length of the
trace. One technique to accomplish this is to change the width
of the traces in a differential pair based on how closely one trace
is coupled to the other. When the two traces of a differential
pair are close and strongly coupled, they should have a width
that produces a 100 Ω differential impedance. When the traces
split apart to go into a connector, for example, and are no longer
so strongly coupled, the width of the traces should be increased
to yield a differential impedance of 100 Ω in the new configuration.
Ground Current Return
In some applications, it can be necessary to invert the output
pin order of the AD8196. This requires a designer to route the
TMDS traces on multiple layers of the PCB. When routing
differential pairs on multiple layers, it is necessary to also re-
route the corresponding reference plane in order to provide one
continuous ground current return path for the differential
signals. An example of this is illustrated in Figure 32.
Figure 32. Example Routing of Reference Plane
TMDS Terminations
The AD8196 provides internal 50 Ω single-ended terminations
for all of its high speed inputs and outputs. It is not necessary to
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PDF描述
AD8196-EVAL 2:1 HDMI/DVI Switch with Equalization
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD8196-EVAL 制造商:AD 制造商全稱:Analog Devices 功能描述:2:1 HDMI/DVI Switch with Equalization
AD8197 制造商:AD 制造商全稱:Analog Devices 功能描述:4:1 HDMI/DVI Switch with Equalization
AD8197A 制造商:AD 制造商全稱:Analog Devices 功能描述:4:1 HDMI/DVI Switch with Equalization
AD8197A_07 制造商:AD 制造商全稱:Analog Devices 功能描述:4:1 HDMI/DVI Switch with Equalization
AD8197AASTZ 功能描述:IC HDMI/DVI SWITCH 4:1 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開(kāi)關(guān)，多路復(fù)用器，多路分解器 系列:- 其它有關(guān)文件:STG4159 View All Specifications 標(biāo)準(zhǔn)包裝:5,000 系列:- 功能:開(kāi)關(guān) 電路:1 x SPDT 導(dǎo)通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:7-覆晶 包裝:帶卷 (TR)
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