參數(shù)資料
型號: AD8191ASTZ
廠商: ANALOG DEVICES INC
元件分類: 運動控制電子
英文描述: 4:1 HDMI/DVI Switch with Equalization
中文描述: 4-CHANNEL, AUDIO/VIDEO SWITCH, PQFP100
封裝: LEAD FREE, MS-026-BED, LQFP-100
文件頁數(shù): 19/32頁
文件大?。?/td> 660K
代理商: AD8191ASTZ
AD8191
SERIAL INTERFACE CONFIGURATION REGISTERS
The serial interface configuration registers can be read and written using the I
2
C serial control interface, Pin I2C_SDA, and Pin I2C_SCL.
The least significant bits of the AD8191 I
2
C part address are set by tying the Pin I2C_ADDR2, Pin I2C_ADDR1, and Pin I2C_ADDR0 to
3.3 V (Logic 1) or 0 V (Logic 0). As soon as the serial control interface is used, the parallel control interface is disabled until the AD8191
is reset as described in the Serial Control Interface section.
Rev. 0 | Page 19 of 32
Table 5. Serial (I
2
C) Interface Register Map
Name
Bit 7
High Speed
Device
Modes
Bit 6
High
speed
switch
enable
HS_EN
Auxiliary
switch
enable
AUX_EN
Bit 5
High speed switching
mode select
Bit 4
Bit 3
Bit 2
High speed source select
Bit 1
Bit 0
Addr.
0x00
Default
0x40
HS_SM[1]
Auxiliary switching
mode select
HS_SM[0]
HS_CH[3]
HS_CH[2]
Auxiliary switch source select
HS_CH[1]
HS_CH[0]
Auxiliary
Device
Modes
AUX_SM[1]
AUX_SM[0]
AUX_CH[3]
AUX_CH[2]
AUX_CH[1]
AUX_CH[0]
High speed
input
termination
select
RX_TO
0x01
0x40
Receiver
Settings
0x10
0x01
Source A and Source B : input termination pulse-on-source switch select
(disconnect termination for a short period of time)
RX_PT[6]
RX_PT[5]
RX_PT[4]
Source C and Source D: input termination pulse-on-source switch select
(disconnect termination for a short period of time)
RX_PT[14]
RX_PT[13]
RX_PT[12]
Source A and Source B: input equalization level select
RX_EQ[6]
RX_EQ[5]
RX_EQ[4]
Source C and Source D: input equalization level select
RX_EQ[14]
RX_EQ[13]
RX_EQ[12]
Input
Termination
Pulse 1
RX_PT[7]
RX_PT[3]
RX_PT[2]
RX_PT[1]
RX_PT [0]
0x11
0x00
Input
Termination
Pulse 2
RX_PT[15]
RX_PT[11]
RX_PT[10]
RX_PT[9]
RX_PT[8]
0x12
0x00
Receive
Equalizer 1
RX_EQ[7]
RX_EQ[3]
RX_EQ[2]
RX_EQ[1]
RX_EQ[0]
0x13
0x00
Receive
Equalizer 2
RX_EQ[15]
RX_EQ[11]
High speed output
pre-emphasis level select
RX_EQ[10]
RX_EQ[9]
High speed
output
termination
select
TX_PTO
RX_EQ[8]
High speed
output
current level
select
TX_OCL
0x14
0x00
Transmitter
Settings
TX_PE[1]
TX_PE[0]
0x20
0x03
HIGH SPEED DEVICE MODES REGISTER
HS_EN: High Speed (TMDS) Channels Enable Bit
Table 6. HS_EN Description
HS_EN
Description
0
High speed channels off, low power/standby mode
1
High speed channels on
HS_SM[1:0]: High Speed (TMDS) Switching Mode
Select Bus
Table 7. HS_SM Description
HS_SM[1:0]
Description
00
Quad mode, 4× [4:1]
01
Dual mode, 2× [8:1]
10
Single mode, 1× [16:1]
11
Illegal value; previous value of HS_SM[1:0]
retained
HS_CH[3:0]: High Speed (TMDS) Switch Source Select Bus
Table 8. Quad Mode, 4× [4:1], High Speed Switch Mapping
HS_CH[3:0]
O[3:0]
Description
XX00
A[3:0]
High Speed Source A switched to
output
XX01
B[3:0]
High Speed Source B switched to
output
XX10
C[3:0]
High Speed Source C switched to
output
XX11
D[3:0]
High Speed Source D switched to
output
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