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參數(shù)資料
| 型號： | AD8190ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/24頁 |
| 文件大小： | 0K |
| 描述： | IC SW HDMI/DVI 2:1 EQUAL 56LFCSP |
| 標準包裝： | 1 |
| 類型： | HDMI/DVI 開關(guān) |
| 應用： | DVI，HDMI 信號開關(guān) |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 托盤 |
AD8190
Rev. 0 | Page 20 of 24
Layout for the TMDS Signals
The TMDS differential pairs can either be microstrip traces,
routed on the outer layer of a board, or stripline traces, routed
on an internal layer of the board. If microstrip traces are used,
there should be a continuous reference plane on the PCB layer
directly below the traces. If stripline traces are used, they must
be sandwiched between two continuous reference planes in the
PCB stack-up. Additionally, the p and n of each differential pair
must have a controlled differential impedance of 100 Ω. The
characteristic impedance of a differential pair is a function of
several variables including the trace width, the distance separating
the two traces, the spacing between the traces and the reference
plane, and the dielectric constant of the PC board binder material.
Interlayer vias introduce impedance discontinuities that can
cause reflections and jitter on the signal path, therefore, it is
preferable to route the TMDS lines exclusively on one layer of the
board, particularly for the input traces. Additionally, to prevent
unwanted signal coupling and interference, route the TMDS
signals away from other signals and noise sources on the PCB.
Both traces of a given differential pair must be equal in length
to minimize intrapair skew. Maintaining the physical symmetry
of a differential pair is integral to ensuring its signal integrity;
excessive intrapair skew can introduce jitter through duty cycle
distortion (DCD). The p and n of a given differential pair should
always be routed together in order to establish the required 100 Ω
differential impedance. Enough space should be left between
the differential pairs of a given group so that the n of one pair
does not couple to the p of another pair. For example, one tech-
nique is to make the interpair distance 4 to 10 times wider than
the intrapair spacing.
Any group of four TMDS channels (Input A, Input B, or the
output) should have closely matched trace lengths in order to
minimize interpair skew. Severe interpair skew can cause the
data on the four different channels of a group to arrive out of
alignment with one another. A good practice is to match the
trace lengths for a given group of four channels to within
0.05 inches on FR4 material.
The length of the TMDS traces should be minimized to re-
duce overall signal degradation. Commonly used PC board
material such as FR4 is lossy at high frequencies, so long traces
on the circuit board increase signal attenuation, resulting in
decreased signal swing and increased jitter through intersymbol
interference (ISI).
Controlling the Characteristic Impedance of a TMDS
Differential Pair
The characteristic impedance of a differential pair depends on a
number of variables including the trace width, the distance
between the two traces, the height of the dielectric material
between the trace and the reference plane below it, and the
dielectric constant of the PCB binder material. To a lesser
extent, the characteristic impedance also depends upon the
trace thickness and the presence of solder mask.
There are many combinations that can produce the correct
characteristic impedance. It is generally required to work with
the PC board fabricator to obtain a set of parameters to produce
the desired results.
One consideration is how to guarantee a differential pair with a
differential impedance of 100 Ω over the entire length of the
trace. One technique to accomplish this is to change the width
of the traces in a differential pair based on how closely one trace
is coupled to the other. When the two traces of a differential
pair are close and strongly coupled, they should have a width
that produces a 100 Ω differential impedance. When the traces
split apart to go into a connector, for example, and are no longer
so strongly coupled, the width of the traces should be increased
to yield a differential impedance of 100 Ω in the new configuration.
TMDS Terminations
The AD8190 provides internal 50 Ω single-ended terminations
for all of its high speed inputs and outputs. It is not necessary to
include external termination resistors for the TMDS differential
pairs on the PCB.
The output termination resistors of the AD8190 back-terminate
the output TMDS transmission lines. These back-terminations
act to absorb reflections from impedance discontinuities on the
output traces, improving the signal integrity of the output traces
and adding flexibility to how the output traces can be routed.
For example, interlayer vias can be used to route the AD8190
TMDS outputs on multiple layers of the PCB without severely
degrading the quality of the output signal.
Auxiliary Control Signals
There are four single-ended control signals associated with each
source or sink in an HDMI/DVI application. These are hot plug
detect (HPD), consumer electronics control (CEC), and two
display data channel (DDC) lines. The two signals on the DDC
bus are SDA and SCL (serial data and serial clock, respectively).
These four signals can be switched through the auxiliary bus of
the AD8190 and do not need to be routed with the same strict
considerations as the high speed TMDS signals.
In general, it is sufficient to route each auxiliary signal as a
single-ended trace. These signals are not sensitive to impedance
discontinuities, do not require a reference plane, and can be
routed on multiple layers of the PCB. However, it is best to
follow strict layout practices whenever possible to prevent the
PCB design from affecting the overall application. The specific
routing of the HPD, CEC, and DDC lines depends upon the
application in which the AD8190 is being used.
For example, the maximum speed of signals present on the
auxiliary lines are 100 kHz I2C data on the DDC lines, therefore,
any layout that enables 100 kHz I2C to be passed over the DDC
bus should suffice. The HDMI 1.2a specification, however,
places a strict 50 pF limit on the amount of capacitance that can
be measured on either SDA or SCL at the HDMI input connector.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8190ACPZ-R7 | 功能描述:IC SW HDMI/DVI 2:1 EQUAL 56LFCSP RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應商設備封裝:400-PBGA（27x27） 包裝:散裝 |
| AD8190-EVAL | 制造商:Analog Devices 功能描述:EVAL BD FOR AD8190 ,2:1 HDMI/DVI SWIT W/ EQUALIZATION - Bulk |
| AD8191 | 制造商:Analog Devices 功能描述:- Bulk |
| AD8191A | 制造商:AD 制造商全稱:Analog Devices 功能描述:4:1 HDMI/DVI Switch with Equalization |
| AD8191AASTZ | 功能描述:IC HDMI/DVI SWITCH 4:1 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復用器，多路分解器 系列:- 其它有關(guān)文件:STG4159 View All Specifications 標準包裝:5,000 系列:- 功能:開關(guān) 電路:1 x SPDT 導通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應商設備封裝:7-覆晶 包裝:帶卷 (TR) |
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