參數(shù)資料
型號(hào)： AD8185
廠商： Analog Devices, Inc.
英文描述： 380 MHz, 25 mA, Triple 2:1 Multiplexers
中文描述： 380兆赫，25毫安，三2:1多路復(fù)用器
文件頁(yè)數(shù)： 12/16頁(yè)
文件大?。?/td> 739K
代理商： AD8185
REV. 0
AD8183/AD8185
–12–
result, the input and output traces, in addition to having a con-
trolled impedance, are well shielded.
SEL
A
/B AND
OE
SEL
A
/B (Pin 22 of the device) allows the A or B inputs to be
selected.
When SEL
A
/B is at logic low, (equal to or less than 0.8 V),
inputs 0A, 1A and 2A are directed to OUTPUTs 0, 1, and 2,
respectively. When SEL
A
/B is at logic high, (equal to or greater
than 2.0 V), inputs 0B, 1B, and 2B are directed to OUTPUTs
0, 1, and 2, respectively.
There are two ways to provide SEL
A
/B to the device: using a
jumper or a BNC connection. With the jumper in the W4 posi-
tion, SEL
A
/B is tied to ground. This selects the A inputs.
With the jumper in the W3 position, SEL
A
/B is tied to 5 V,
through pull up resistor R15. This selects the B inputs.
If faster use of SEL
A
/B is desired, the 50
BNC connector at
J10 can be used. If J10 is used, there must NOT be a jumper on
W3 and W4. Microstrip line techniques provide a 50
charac-
teristic impedance from J10 to the device. Please refer to Figure
Figure 42.Evaluation Board Schematic
41 for the arrangement of the PCB layers. If J10 is used, the
user may wish to install a 50
termination resistor at R10.
OE
(Pin 23 of the device) allows the three outputs to be enabled
or disabled. When
OE
is at logic low, (equal to or less than
0.8 V), Outputs 0, 1, and 2 are enabled. When
OE
is at logic
high, (equal to or greater than 2.0 V), Outputs 0, 1, and 2 are
disabled (placed into a high impedance state).
Once again, there are two different ways to provide
OE
to the
device: using a jumper or a BNC connection. With the jumper
in the W2 position,
OE
is tied to ground. This enables the outputs.
With the jumper in the W1 position,
OE
is tied to 5 V, through
pull-up resistor R16. This selects “Hi Z,” or high impedance,
and the outputs are disabled.
If faster use of
OE
is desired, the 50
BNC connector at J11
can be used. If J11 is used, there must NOT be a jumper on W1
and W2. Microstrip line techniques provide a 50
characteris-
tic impedance from J11 to the device. Please refer to Figure 41
for the arrangement of the PCB layers. If J11 is used, the user
may wish to install a 50
termination resistor at R11.
IN0A
DGND
IN1A
AGND
IN2A
V
CC
V
EE
IN2B
AGND
IN1B
AGND
IN0B
V
CC
OE
SEL
A
/B
V
CC
OUT0
V
EE
OUT1
V
CC
OUT2
V
EE
DVCC
V
CC
AD8183/
AD8185
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DGND
AGND
AGND
AGND
C8
0.01
m
F
AGND
C7
0.01
m
F
AGND
V
CC
V
EE
75
V
STRIPLINE
R3
75
V
AGND
J3
IN2A
75
V
STRIPLINE
R2
75
V
AGND
J2
IN1A
75
V
STRIPLINE
R1
75
V
AGND
J1
IN0A
75
V
STRIPLINE
R6
75
V
AGND
J6
IN0B
75
V
STRIPLINE
R5
75
V
AGND
J5
IN1B
75
V
STRIPLINE
R4
75
V
AGND
J4
IN2B
W5
AGND
DGND
C9
m
F
AGND
C10
m
F
DGND
C11
m
F
AGND
V
EE
DVCC
V
CC
C12
m
F
AGND
V
CC
C13
m
F
AGND
V
EE
C14
0.01
m
F
AGND
V
CC
R10
50
V
OPTIONAL
DGND
R13
75
V
J8
OUT1
75
V
STRIPLINE
R12
75
V
J7
OUT2
75
V
STRIPLINE
R14
75
V
J9
OUT0
75
V
STRIPLINE
50
V
MICROSTRIP LINE
DGND
W4
W3
R15
20k
V
V
CC
SEL
A
/B
J10
C15
m
F
AGND
V
CC
R11
50
V
OPTIONAL
DGND
50
V
MICROSTRIP LINE
DGND
W2
W1
R16
V
V
CC
OE
J11
OE
P1
DVCC
1
C3
10
m
F
DGND
+
DVCC
C6
0.1
m
F
DGND
DVCC
P1
DGND
2
DGND
DGND
P1
V
EE
4
C2
10
m
F
AGND
+
V
EE
C5
0.1
m
F
AGND
V
EE
P1
AGND
5
AGND
AGND
P1
V
CC
6
C1
10
m
F
AGND
+
V
CC
C4
0.1
m
F
AGND
V
CC
SEL
A
/B
DUT
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