參數(shù)資料
型號(hào)： AD8178ABPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 26/40頁(yè)
文件大?。?/td> 0K
描述： IC VIDEO CROSSPOINT SWIT 676BGA
標(biāo)準(zhǔn)包裝： 1
功能： 視頻交叉點(diǎn)開關(guān)
電路： 3 x 16:5
電壓電源： 單/雙電源
電壓 - 電源，單路/雙路(±)： 4.5 V ~ 5.5 V，±2.5V
電流 - 電源： 460mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 676-BGA
供應(yīng)商設(shè)備封裝： 676-BGA（27x27）
包裝： 管件
AD8178
Rev. 0 | Page 32 of 40
At low frequencies, this is a negligible component of crosstalk,
but PSRR falls off as frequency increases. With differential,
balanced loads, as one output draws current from the positive
supply, the other output draws current from the negative supply.
When the phase alternates, the first output draws current from
the negative supply and the second draws from the positive
supply. The effect is that a more constant current is drawn from
each supply, such that the crosstalk-inducing supply fluctuation
is minimized.
A third benefit of driving balanced loads is that the output pulse
response changes as the load changes. The differential signal
control loop in the AD8178 forces the difference of the outputs
to be a fixed ratio to the difference of the inputs. If the two
output responses are different due to loading, this creates a
difference that the control loop sees as signal response error, and
it attempts to correct this error. This distorts the output signal
from the ideal response compared to the case when the two
outputs are balanced.
Decoupling
The signal path of the AD8178 is based on high open-loop gain
amplifiers with negative feedback. Dominant-pole compensation
is used on-chip to stabilize these amplifiers over the range of
expected applied swing and load conditions. To guarantee this
designed stability, proper supply decoupling is necessary with
respect to both the differential control loops and the common-
mode control loops of the signal path. Signal-generated currents
must return to their sources through low impedance paths at all
frequencies in which there is still loop gain (up to 700 MHz at
a minimum).
The signal path compensation capacitors in the AD8178 are
connected to the VNEG supply. At high frequencies, this limits
the power supply rejection ratio (PSRR) from the VNEG supply
to a lower value than that from the VPOS supply. If given a
choice, an application board should be designed such that the
VNEG power is supplied from a low inductance plane, subject
to a least amount of noise.
VOCM_CMENCON and VOCM_CMENCOFF are high speed
common-mode control loops of all output drivers. In the single-
ended output sense, there is no rejection from noise on these
inputs to the outputs. For this reason, care must be taken to
produce low noise sources over the entire range of frequencies
of interest. This is important not only to single-ended operation,
but to differential operation, because there is a common-mode-
to-differential gain conversion that becomes greater at higher
frequencies.
VOCM_CMENCON and VOCM_CMENCOFF are internally
buffered to prevent transients flowing into or out of these inputs
from acting on the source impedance and becoming sources of
crosstalk.
Power Dissipation
Calculation of Power Dissipation
06
60
8-
02
5
AMBIENT TEMPERATURE (°C)
MA
X
IMU
M
D
IE
P
O
W
E
R
(W
)
3
4
5
6
7
8
9
10
15
25
35
45
55
65
75
85
TJ = 150°C
Figure 50. Maximum Die Power Dissipation vs. Ambient Temperature
The curve in Figure 50 was calculated from
JA
AMBIENT
MAX
JUNCTION
MAX
D
T
P
θ
=
,
(1)
As an example, if the AD8178 is enclosed in an environment at
45°C (TA), the total on-chip dissipation under all load and supply
conditions must not be allowed to exceed 7.0 W.
When calculating on-chip power dissipation, it is necessary to
include the power dissipated in the output devices due to current
flowing in the loads. For a sinusoidal output about ground and
symmetrical split supplies, the on-chip power dissipation due to
the load can be approximated by
PD,OUTPUT = (VPOS VOUTPUT,RMS) × IOUTPUT,RMS
(2)
For nonsinusoidal output, the power dissipation should be
calculated by integrating the on-chip voltage drop across the
output devices multiplied by the load current over one period.
The user can subtract the quiescent current for the Class AB
output stage when calculating the loaded power dissipation. For
each output stage driving a load, subtract a quiescent power,
according to
PDQ,OUTPUT = (VPOS VNEG) × IOUTPUT,QUIESCENT
(3)
where IOUTPUT, QUIESCENT = 1.65 mA for each single-ended output
pin of the AD8178.
For each disabled RGB output channel, the quiescent power supply
current in VPOS and VNEG drops by approximately 34 mA.
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