![](http://datasheet.mmic.net.cn/Analog-Devices-Inc/AD8176ABPZ_datasheet_95934/AD8176ABPZ_32.png)
AD8176
Rev. 0 | Page 32 of 40
magnetic fields do not couple equally into adjacent output pairs
due to different proximities, but they do destructively cancel the
crosstalk to some extent. If the load current in each output is
equal, this cancellation is greater and less adjacent crosstalk is
observed (regardless of whether the second output is actually
being used).
A second benefit of balancing the output loads in a differential
pair is to reduce fluctuations in current requirements from the
power supply. In single-ended loads, the load currents alternate
from the positive supply to the negative supply. This creates a
parasitic signal voltage in the supply pins due to the finite
resistance and inductance of the supplies. This supply fluctuation
appears as crosstalk in all outputs, attenuated by the power
supply rejection ratio (PSRR) of the device. At low frequencies,
this is a negligible component of crosstalk, but PSRR falls off as
frequency increases. With differential, balanced loads, as one
output draws current from the positive supply, the other output
draws current from the negative supply. When the phase
alternates, the first output draws current from the negative
supply and the second from the positive supply. The effect is
that a more constant current is drawn from each supply, such
that the crosstalk-inducing supply fluctuation is minimized.
A third benefit of driving balanced loads can be seen if one
considers that the output pulse response changes as load
changes. The differential signal control loop in the AD8176
forces the difference of the outputs to be a fixed ratio to the
difference of the inputs. If the two output responses are different
due to loading, this creates a difference that the control loop
sees as signal response error, and it attempts to correct this
error. This distorts the output signal from the ideal response
compared to the case when the two outputs are balanced.
Decoupling
The signal path of the AD8176 is based on high open-loop gain
amplifiers with negative feedback. Dominant-pole compensation
is used on-chip to stabilize these amplifiers over the range of
expected applied swing and load conditions. To guarantee this
designed stability, proper supply decoupling is necessary with
respect to both the differential control loops and the common-
mode control loops of the signal path. Signal-generated currents
must return to their sources through low impedance paths at all
frequencies in which there is still loop gain (up to 700 MHz at a
minimum).
The signal path compensation capacitors in the AD8176 are
connected to the VNEG supply. At high frequencies, this limits
the power supply rejection ratio (PSRR) from the VNEG supply
to a lower value than that from the VPOS supply. If given a
choice, an application board should be designed such that the
VNEG power is supplied from a low inductance plane, subject
to a least amount of noise.
VOCM_CMENCON and VOCM_CMENCOFF are high speed
common-mode control loops of all output drivers. In the single-
ended output sense, there is no rejection from noise on these
inputs to the outputs. For this reason, care must be taken to
produce low noise sources over the entire range of frequencies
of interest. This is not only important to single-ended operation,
but to differential operation, as there is a common-mode-to-
differential gain conversion that becomes greater at higher
frequencies.
VOCM_CMENCON and VOCM_CMENCOFF are internally
buffered to prevent transients flowing into or out of these inputs
from acting on the source impedance and becoming sources of
crosstalk.
Power Dissipation
Calculation of Power Dissipation
06
59
6-
0
24
AMBIENT TEMPERATURE (°C)
MA
X
IMU
M
P
O
W
E
R
(
W
)
3
4
5
6
7
8
9
10
15
25
35
45
55
65
75
85
TJ = 150°C
Figure 50. Maximum Die Power Dissipation vs. Ambient Temperature
JA
AMBIENT
MAX
JUNCTION
MAX
D
T
P
θ
=
,
(2)
As an example, if the AD8176 is enclosed in an environment at
45°C (TA), the total on-chip dissipation under all load and
supply conditions must not be allowed to exceed 7.0 W.
When calculating on-chip power dissipation, it is necessary to
include the power dissipated in the output devices due to
current flowing in the loads. For a sinusoidal output about
ground and symmetrical split supplies, the on-chip power
dissipation due the load can be approximated by
(
)
RMS
OUTPUT
RMS
UTPUT
O
POS
OUTPUT
D
I
V
P
,
×
=
(3)
For nonsinusoidal output, the power dissipation should be
calculated by integrating the on-chip voltage drop across the
output devices multiplied by the load current over one period.
The user can subtract the quiescent current for the Class AB
output stage when calculating the loaded power dissipation. For
each output stage driving a load, subtract a quiescent power,
according to
(
)
QUIESCENT
OUTPUT
NEG
POS
OUTPUT
DQ
I
V
P
,
×
=
(4)
where IOUTPUT, QUIESCENT = 1.65 mA for each single-ended output
pin for the AD8176.