- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1892 > AD8152JBP (Analog Devices Inc)IC CROSSPOINT SWIT 34X34 256BGA PDF資料下載
參數(shù)資料
| 型號： | AD8152JBP |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/32頁 |
| 文件大小： | 0K |
| 描述： | IC CROSSPOINT SWIT 34X34 256BGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | XStream™ |
| 功能： | 交叉點(diǎn)開關(guān) |
| 電路： | 1 x 34:34 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 2.25 V ~ 3.63 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-LBGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 256-SBGA（27x27） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
REV. A
–16–
AD8152
RESET
DISABLING
OUT[0:33][N:P]
OUTPUTS
tTOD
tTW
Figure 5. Asynchronous Reset
Table IX. Asynchronous Reset
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tTOD
Disable Time
Output Disable from Reset
TA = 25 C10
25ns
tTW
Width of Reset Pulse
VCC = 3.3 V
10
ns
CONTROL INTERFACE
The AD8152 control interface receives and stores the desired
connection matrix and output levels for the 34 input and 34 output
signal pairs. The interface consists of 34 rows of double-rank
6-bit latches, one for each output. The 6-bit data-word stored
in these latches indicates to which (if any) of the 34 inputs the
output will be connected, as well as the full-scale output current.
One output at a time can be preprogrammed by addressing the
output and writing the desired connection data or output cur-
rent into the first rank of latches. This process can be repeated
until each of the desired output changes has been preprogrammed.
All output connections can then be programmed at once by passing
the data from the first rank of latches into the second rank. The
output connections always reflect the data programmed into the
second rank of latches and do not change until the first rank of
data is passed into the second rank.
If necessary for system verification, the data in the second rank
of latches can be read back from the control interface.
At any time, a reset pulse can be applied to the control interface to
globally reset the appropriate second rank data bits, disabling all 34
signal output pairs and resetting the output currents. To facilitate
multiple chip address decoding, there is a chip select pin. All logic
signals except the reset pulse are ignored unless the chip select
pin is active. The chip select pin disables only the control logic
interface and does not change the operation of the signal matrix.
The chip select pin does not power down any of the latches, so any
data programmed in the latches is preserved.
All control pins are level-sensitive, not edge-triggered.
CONTROL PIN DESCRIPTION
A[6:0] Inputs
Output address pins. The binary encoded address applied to the
lower A[5:0] input pins determines which of the 34 outputs is
being programmed (or being read back). The most significant bit,
A6, determines whether the data pins contain information for
the connection register bank or the output level register bank.
Using the broadcast address, A[5:0] = “111111” will simulta-
neously program data into all outputs at once.
D[5:0] Inputs/Outputs
Input configuration or output level data pins. In write mode,
when the bank selection bit A6 is LOW, the binary encoded data
applied to pins D[5:0] determine which of the 34 inputs is to be
connected to the output specified with the A[5:0] pins. The most
significant bit is D5, and the least significant bit is D0. To disable
an output completely, the input address D[5:0] = “111111”
should be written into the input configuration bank at the desired
output address.
In write mode, when the bank selection bit A6 is HIGH, the
binary encoded data applied to pins D[3:0] indicate the output
current level to be used for the output specified with the A[5:0]
pins. The reset default is “0111” for 16 mA. Each LSB is 2 mA.
In readback mode, pins D[5:0] are low impedance outputs
indicating the data-word stored in the second rank for the out-
put specified with the A[5:0] pins and the bank specified with
the A6 bit. The readback drivers were designed to drive high
impedances only, so external drivers connected to the D[5:0]
should be disabled during readback mode.
WE Input
First rank write enable. Forcing this pin to logic low allows the
data on pins D[5:0] to be stored in the first rank latch for the
output specified by pins A[6:0]. The
WE pin must be returned to a
logic high state after a write cycle to avoid overwriting the first
rank data.
UPDATE Input
Second rank write enable. Forcing this pin to logic low allows the
data stored in all 34 first rank latches (in both banks) to be trans-
ferred to the second rank latches. The signal connection matrix
will be reprogrammed when the second rank data and levels are
changed. This is a global pin, transferring all 34 rows of data at
once. It is not necessary to program the address pins. It should
be noted that after initial power-up of the device, the first rank
data is undefined. It is desirable to preprogram all 17 outputs
before performing the first update cycle.
RE Input
Second rank read enable. Forcing this pin to logic low enables the
output drivers on the bidirectional D[5:0] pins, entering the read-
back mode of operation. By selecting an output address with the
A[6:0] pins and forcing
RE to logic low, the 6-bit data stored in
the second rank latch for that output address will be written to
D[5:0] pins. Data should not be written to the D[5:0] pins
externally while in readback mode. The
RE is a higher priority
pin than the
WE pin, so first rank programming is not possible
while in readback mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD8153ACPZ-RL7 | IC SW MUX/DEMUX SGL BUFF 32LFCSP |
| AD8155ACPZ | IC MUX/DEMUX DUAL BUFFER 64LFCSP |
| AD8156ABCZ | IC SWITCH XPT 4X4 W/EQ 49CSPBGA |
| AD8158ACPZ | IC MUX/DEMUX QUAD 2X1 100LFCSP |
| AD8159ASVZ | IC MUX/DEMUX QUAD BUFF 100TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8152JBPZ | 功能描述:IC CROSSPOINT SWIT 34X34 256BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:XStream™ 應(yīng)用說明:Ultrasound Imaging Systems Application Note 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 功能:開關(guān) 電路:單刀單擲 導(dǎo)通狀態(tài)電阻:48 歐姆 電壓電源:單電源 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電流 - 電源:5µA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:托盤 |
| AD8153 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3.2 Gbps Single Buffered Mux/Demux Switch |
| AD8153_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3.2 Gbps Single Buffered Mux/Demux Switch |
| AD8153ACPZ | 功能描述:IC SW MUX/DEMUX SGL BUFF 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:XStream™ 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD8153ACPZ-RL7 | 功能描述:IC SW MUX/DEMUX SGL BUFF 32LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:XStream™ 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。