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參數(shù)資料
| 型號(hào)： | AD8092ARZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP VF R-R DUAL LDIST 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 放大器類型： | 電壓反饋 |
| 電路數(shù)： | 2 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 170 V/µs |
| -3db帶寬： | 110MHz |
| 電流 - 輸入偏壓： | 1.4µA |
| 電壓 - 輸入偏移： | 1800µV |
| 電流 - 電源： | 4.8mA |
| 電流 - 輸出 / 通道： | 45mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 12 V，±1.5 V ~ 6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
AD8091/AD8092
Rev. C | Page 7 of 20
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8091/AD8092
package is limited by the associated rise in junction temperature
(TJ) on the die. The plastic encapsulating the die locally reaches
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8091/AD8092.
Exceeding a junction temperature of 175°C for an extended
period of time can result in changes in the silicon devices,
potentially causing failure.
The still-air thermal properties of the package (θJA), the ambient
temperature (TA), and the total power dissipated in the package
(PD) can be used to determine the junction temperature of the die.
The junction temperature can be calculated as
(
)
JA
D
A
J
θ
P
T
×
+
=
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming that the load (RL) is referenced
to midsupply, then the total drive power is VS/2 × IOUT, some of
which is dissipated in the package and some in the load
(VOUT × IOUT). The difference between the total drive power and
the load power is the drive power dissipated in the package.
(
)
power
load
power
drive
total
power
quiescent
PD
+
=
()
×
+
×
=
L
OUT
L
OUT
S
D
R
V
R
V
I
V
P
2
RMS output voltages should be considered. If RL is referenced to
VS, as in single-supply operation, then the total drive power is
VS × IOUT.
If the rms signal levels are indeterminate, then consider the
worst case when VOUT = VS/4 for RL to midsupply
()
2
4
L
S
D
R
V
I
V
P
+
×
=
In single-supply operation with RL referenced to VS, the worst
case is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. Also,
more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes reduces
the θJA. Care must be taken to minimize parasitic capacitances
at the input leads of high speed op amps as discussed in the
Input Capacitance section.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the SOIC-8
(125°C/W), SOT23-5 (180°C/W), and MSOP-8 (150°C/W) on a
JEDEC standard four-layer board.
2.0
0
0.5
1.0
1.5
–40 –30 –20 –10
0
10
20
30
40
50
60
70
80
90
02
85
9-
00
4
AMBIENT TEMPERATURE (°C)
M
A
XI
M
U
M
PO
W
E
R
D
ISSI
P
A
T
IO
N
(W
)
TJ = 150°C
MSOP-8
SOIC-8
SOT23-5
Figure 4. Maximum Power Dissipation vs.
Temperature for a Four-Layer Board
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