參數(shù)資料
型號(hào)： AD8061ARZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/20頁(yè)
文件大?。?/td> 0K
描述： IC OPAMP VF R-R LP 50MA 8SOIC
標(biāo)準(zhǔn)包裝： 2,500
放大器類型： 電壓反饋
電路數(shù)： 1
輸出類型： 滿擺幅
轉(zhuǎn)換速率： 650 V/µs
-3db帶寬： 320MHz
電流 - 輸入偏壓： 3.5µA
電壓 - 輸入偏移： 1000µV
電流 - 電源： 6.8mA
電流 - 輸出 / 通道： 50mA
電壓 - 電源，單路/雙路(±)： 2.7 V ~ 8 V，±1.35 V ~ 4 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SO
包裝： 帶卷 (TR)
Data Sheet
AD8061/AD8062/AD8063
Rev. J | Page 15 of 20
TIME (ns)
2.0
0
OU
TP
U
T
V
O
LT
A
G
E
(V)
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
4
8
12
16
20
24
28
32
2V TO 3V STEP
2.1V TO 3.1V STEP
2.2V TO 3.2V STEP
2.3V TO 3.3V STEP
2.4V TO 3.4V STEP
01065-
047
Figure 47. Output Rising Edge for 1 V Step at
Input Headroom Limits, G = 1, VS = 5 V, 0 V
As the saturation point of the output stage is approached, the
output signal shows increasing amounts of compression and
clipping. As in the input headroom case, the higher frequency
signals require a bit more headroom than lower frequency
signals. Figure 16, Figure 17, and Figure 18 illustrate this point,
plotting typical distortion vs. output amplitude and bias for
gains of 2 and 5.
OVERLOAD BEHAVIOR AND RECOVERY
Input
The specified input common-mode voltage of the AD8061/
AD8062/AD8063 is 200 mV below the negative supply to
within 1.8 V of the positive supply. Exceeding the top limit
results in lower bandwidth and increased settling time as seen
in Figure 46 and Figure 47. Pushing the input voltage of a unity-
gain follower beyond 1.6 V within the positive supply leads to
the behavior shown in Figure 48—an increasing amount of
output error and much increased settling time. Recovery time
from input voltages 1.6 V or closer to the positive supply is
approximately 35 ns, which is limited by the settling artifacts
caused by transistors in the input stage coming out of saturation.
The AD8061/AD8062/AD8063 family does not exhibit phase
reversal, even for input voltages beyond the voltage supply rails.
Going more than 0.6 V beyond the power supplies turns on
protection diodes at the input stage, which greatly increases the
current draw of the device.
TIME (ns)
2.1
0
OU
TP
U
T
V
O
LT
A
G
E
(V)
2.3
100
VOLTAGE STEP
FROM 2.4V TO 3.4V
2.5
2.7
2.9
3.1
3.3
3.5
3.7
VOLTAGE STEP
FROM 2.4V TO 3.6V
VOLTAGE STEP
FROM 2.4V TO 3.8V,
4V AND 5V
200
300
400
500
600
01065-
048
Figure 48. Pulse Response for G = 1 Follower,
Input Step Overloading the Input Stage
Output
Output overload recovery is typically within 40 ns after the
amplifier’s input is brought to a nonoverloading value. Figure 49
shows output recovery transients for the amplifier recovering
from a saturated output from the top and bottom supplies to a
point at midsupply.
TIME (ns)
–0.2
INP
UT
AND
O
UT
P
UT
V
O
LT
A
G
E
(V)
OUTPUT VOLTAGE
5V TO 2.5V
0.2
0.6
1.0
1.4
1.8
2.2
2.6
3.0
3.4
3.8
4.2
4.6
5.0
10
20
30
40
50
60
70
OUTPUT VOLTAGE
0V TO 2.5V
INPUT VOLTAGE
EDGES
R
5V
VO
2.5V
R
VIN
–
0
01065-
049
Figure 49. Overload Recovery, G = 1, VS = 5 V
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