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參數(shù)資料
| 型號(hào)： | AD8012AR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | SB 2- 7/9 |
| 中文描述： | 1 CHANNEL, VIDEO AMPLIFIER, PDSO8 |
| 封裝： | MS-012AA, SOIC-8 |
| 文件頁(yè)數(shù)： | 13/15頁(yè) |
| 文件大?。?/td> | 414K |
| 代理商： | AD8012AR |
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AD8012
–13–
REV. A
Choosing the Appropriate Turns Ratio for the Transformer
Increasing the peak-to-peak output signal from the amplifier in
the previous example, combined with a variation in the turns
ratio of the transformer, can yield further enhancements to the
circuit. The output signal swing of the AD8012 can be increased
to about
±
3.9 V before clipping occurs. This increases the peak-
to-peak output of the differential amplifier to 15.6 V. Because
the signal applied to the primary winding is now bigger, the
transformer turns ratio of 1:1 can be replaced with a (step-
down) turns ratio of about 1.3:1 (from amplifier to line). This
steps the 7.8 V peak-to-peak primary voltage down to 6 V. This
is the same secondary voltage as before so the resulting power
delivered to the line is the same.
The received signal, which is small relative to the transmitted
signal, will, however be stepped
up
by a factor of 1.3. Amplifying
the received signal in this manner enhances its signal-to-noise
ratio and is useful when the received signal is small compared to
the to-be-transmitted signal.
The impedance reflected from the 135
line now becomes
228
(1.3
2
times 135
). With a correctly terminated line, the
amplifier must now drive a total load of 456
(114
+ 114
+ 228
), considerably less than the original 270
load. This
reduces the drive current from the op amps by about 40%.
More significant however is the reduction in dynamic power
consumption; that is, the power the amplifier must consume in
order to deliver the load power. Increasing the output signal so
that it is as close as possible to the power rails, minimizes the
power consumed in the amplifier.
There is, however, a price to pay in terms of increased signal
distortion. Increasing the output signal of each op amp from the
original
±
3 V to
±
3.9 V reduces the Spurious Free Dynamic
Range (SFDR) from –65 dB to –50 dB (measured at 500 kHz),
even though the overall load impedance has increased from
270
to 456
.
LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8012 requires
careful attention to board layout and component selection.
Table I shows recommended component values for the AD8012
and Figures 44–49 show recommended layouts for the 8-lead
SOIC and microSOIC packages for a positive gain. Proper RF
design techniques and low parasitic component selections are
mandatory.
Table I. Typical Bandwidth vs. Gain Setting Resistors
Small Signal –3 dB BW (MHz),
V
S
=
6
5 V, R
L
= 1 k
V
Gain
R
F
R
G
R
T
–1
+1
+2
+10
750
750
750
750
750
–
750
82.5
53.6
49.9
49.9
49.9
110
350
150
40
R
T
chosen for 50
characteristic input impedance.
The PCB should have a ground plane covering all unused por-
tions of the component side of the board to provide a low im-
pedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing (see Fig-
ure 43). One end should be connected to the ground plane
and the other within 1/8 in. of each power pin. An additional
(4.7
μ
F–10
μ
F) tantalum electrolytic capacitor should be con-
nected in parallel.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance greater than 1.5 pF at the inverting
input will significantly affect high speed performance when
operating at low noninverting gains.
Stripline design techniques should be used for long signal traces
(greater than about 1 in.). These should be designed with the
proper system characteristic impedance and be properly termi-
nated at each end.
0.1
m
F
INVERTING CONFIGURATION
V
OUT
R
F
R
O
*
10
m
F
+
NONINVERTING CONFIGURATION
V
OUT
R
G
R
F
R
O
*
R
T
0.1
m
F
10
m
F
R
T
V
IN
R
G
V
IN
*R
O
CHOSEN FOR CHARACTERISTIC IMPEDANCE.
*R
O
CHOSEN FOR CHARACTERISTIC IMPEDANCE.
+V
S
+
–V
S
Figure 43. Inverting and Noninverting Configurations
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD8012AR-REEL | Dual 350 MHz Low Power Amplifier |
| AD8012AR-REEL7 | Dual 350 MHz Low Power Amplifier |
| AD8012ARM | Dual 350 MHz Low Power Amplifier |
| AD8012ARM-REEL | Dual 350 MHz Low Power Amplifier |
| AD8012ARM-REEL7 | Dual 350 MHz Low Power Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8012AR | 制造商:Analog Devices 功能描述:AMPLIFIER ((NW)) |
| AD8012AR-EBZ | 功能描述:BOARD EVAL FOR AD8012AR RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 運(yùn)算放大器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- |
| AD8012ARM | 功能描述:IC OPAMP CF DUAL LP 125MA 8MSOP RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 放大器類型:J-FET 電路數(shù):2 輸出類型:- 轉(zhuǎn)換速率:13 V/µs 增益帶寬積:3MHz -3db帶寬:- 電流 - 輸入偏壓:65pA 電壓 - 輸入偏移:3000µV 電流 - 電源:1.4mA 電流 - 輸出 / 通道:- 電壓 - 電源，單路/雙路(±):7 V ~ 36 V，±3.5 V ~ 18 V 工作溫度:-40°C ~ 85°C 安裝類型:通孔 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 |
| AD8012ARM-EBZ | 功能描述:BOARD EVAL FOR AD8012ARM RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 運(yùn)算放大器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- |
| AD8012ARM-REEL | 制造商:Analog Devices 功能描述:ADSL Driver Dual 8-Pin MSOP T/R |
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