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| 型號： | AD8004AR-14 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP CF QUAD LP LDIST 14SOIC |
| 標準包裝： | 56 |
| 放大器類型： | 電流反饋 |
| 電路數(shù)： | 4 |
| 轉(zhuǎn)換速率： | 3000 V/µs |
| -3db帶寬： | 250MHz |
| 電流 - 輸入偏壓： | 40µA |
| 電壓 - 輸入偏移： | 1000µV |
| 電流 - 電源： | 14mA |
| 電流 - 輸出 / 通道： | 50mA |
| 電壓 - 電源，單路/雙路(±)： | 4 V ~ 12 V，±2 V ~ 6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-SOIC |
| 包裝： | 管件 |
REV. C
AD8004
–10–
DRIVING CAPACITIVE LOADS
The AD8004 was designed primarily to drive nonreactive loads.
If driving loads with a capacitive component is desired, best
settling response is obtained by the addition of a small series
resistance as shown in Figure 6. The accompanying graph shows
the optimum value for RSERIES vs. capacitive load. It is worth
noting that the frequency response of the circuit when driving
large capacitive loads will be dominated by the passive roll-off of
RSERIES and CL.
1k
RL
1k
CL
AD8004
RSERIES
1k
Figure 6. Driving Capacitive Load
40
30
20
010
15
20
25
CL – pF
10
R
SERIES
–
5
Figure 7. Recommended RSERIES vs. Capacitive Load for
30 ns Settling to 0.1%
OPTIMIZING FLATNESS
The fine scale gain flatness and –3 dB bandwidth is affected by
RFEEDBACK selection as is normal of current feedback amplifiers.
With the exception of gain = +1, the AD8004 can be adjusted
for either maximal flatness with modest closed-loop bandwidth
or for mildly peaked-up frequency response with much more
bandwidth. Figure 8 shows the effect of three evenly spaced RF
changes upon gain = +1 and gain = +2. Table I shows the
recommended component values for achieving maximally flat
frequency response as well as a faster slightly peaked-up fre-
quency response.
Printed circuit board parasitics and device lead frame parasitics
also control fine scale gain flatness. The AD8004R package,
because of its small lead frame, offers superior parasitics relative
to the N package. In the printed circuit board environment,
parasitics such as extra capacitance caused by two parallel and
vertical flat conductors on opposite PC board sides in the
region of the summing junction will cause some bandwidth
extension and/or increased peaking. In noninverting gains, the
effect of extra capacitance on summing junctions is far more
pronounced than with inverting gains. Figure 9 shows an example
of this. Note that only 1 pF of added junction capacitance causes
about a 70% bandwidth extension and additional peaking on a
gain = +2. For an inverting gain = –2, 5 pF of additional summing
junction capacitance caused a small 10% bandwidth extension.
Extra output capacitive loading also causes bandwidth exten-
sions and peaking. The effect is more pronounced with less
resistive loading from the next stage. Figure 10 shows the effect
of direct output capacitive loads for gains of +2 and –2. For both
gains CLOAD was set to 10 pF or 0 pF (no extra capacitive loading).
For each of the four traces in Figure 10 the resistive loads were
100
. Figure 11 also shows capacitive loading effects with a
lighter output resistive load. Note that even though bandwidth
is extended 2
, the flatness dramatically suffers.
FREQUENCY – MHz
–2
1
500
10
40
100
1
0
–1
VIN = 50mV rms
VS = 5V
RL = 100
R PACKAGE
–3
–4
–5
NORMALIZED
GAIN
–
dB,
G
=
+2
2
–3
0
1
–1
–2
–4
–5
–6
RF = 1.10k
RF = 604
G = +1
G = +2
–7
–8
GAIN
–
dB,
G
=
+1
RF = 845
RF = 909
RF = 1.1k
RF = 698
Figure 8. RFEEDBACK vs. Frequency Response, G = +1/+2
FREQUENCY – MHz
2
–8
1
500
10
40
100
–2
0
–4
–6
VIN = 50mV rms
RL = 100
5VS
–10
–12
–14
NORMALIZED
GAIN
–
dB,
G
=
–2
NORMALIZED
GAIN
–
dB,
G
=
+2
2
–8
–2
0
–4
–6
–10
–12
–14
CJ = 1pF
CJ = 0
CJ = 5.1pF
CJ = 0
G = +2
G = –2
Figure 9. Frequency Response vs. Added Summing
Junction Capacitance
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