the I
參數(shù)資料
型號(hào): AD7995YRJZ-0500RL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 15/28頁(yè)
文件大小: 0K
描述: IC ADC 10BIT 4CH SAR I2C SOT23-8
產(chǎn)品變化通告: AD7991,5,9 Offset Error Change 17/Sept/2010
設(shè)計(jì)資源: Using AD8599 as an Ultralow Distortion Driver for the AD7995 (CN0044)
標(biāo)準(zhǔn)包裝: 1
位數(shù): 10
采樣率(每秒): 1M
數(shù)據(jù)接口: I²C,串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 4.68mW
電壓電源: 單電源
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-8
供應(yīng)商設(shè)備封裝: SOT-23-8
包裝: 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型: 4 個(gè)單端,單極
產(chǎn)品目錄頁(yè)面: 780 (CN2011-ZH PDF)
配用: EVAL-AD7995EBZ-ND - BOARD EVAL FOR AD7995
其它名稱: AD7995YRJZ-0500RL7DKR
AD7991/AD7995/AD7999
Rev. B | Page 22 of 28
SERIAL INTERFACE
Control of the AD7991/AD7995/AD7999 is accomplished via
the I2C-compatible serial bus. The AD7991/AD7995/AD7999 is
connected to this bus as a slave device under the control of a
master device, such as the processor.
SERIAL BUS ADDRESS
Like all I2C-compatible devices, the AD7991/AD7995/AD7999 has
a 7-bit serial address. The devices are available in two versions, the
AD7991-0/AD7995-0 and the AD7991-1/AD7995-1/AD7999-1.
Each version has a different address (see Table 8), which allows up
to two AD7991/AD7995 devices to be connected to a single
serial bus. AD7999 has only one version.
The serial bus protocol operates as follows:
1.
The master initiates a data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line SDA while the serial clock line, SCL, remains high.
This indicates that an address/data stream follows.
2.
All slave peripherals connected to the serial bus respond to
the start condition and shift in the next eight bits, consisting of
a 7-bit address (MSB first) plus an R/W bit that determines
the direction of the data transfer—that is, whether data is
written to or read from the slave device.
3.
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the
low period before the ninth clock pulse, known as the
acknowledge bit. All other devices on the bus remain idle
while the selected device waits for data to be read from or
written to it. If the R/W bit is set to 0, the master writes to
the slave device. If the R/W bit is set to 1, the master reads
from the slave device.
4.
Data is sent over the serial bus in sequences of nine clock
pulses—eight bits of data followed by an acknowledge bit
from the receiver of data. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period because a low-to-high transition
when the clock is high may be interpreted as a stop signal.
5.
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the 10th clock pulse to assert a stop condition.
In read mode, the master device pulls the data line high
during the low period before the ninth clock pulse. This is
known as a no acknowledge. The master takes the data line
low during the low period before the 10th clock pulse, and
then high during the 10th clock pulse to assert a stop condition.
6.
Any number of bytes of data can be transferred over the serial
bus in one operation, but it is not possible to mix reads and
writes in one operation because the type of operation is
determined at the beginning and cannot subsequently be
changed without starting a new operation.
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