參數(shù)資料
型號： AD7952BCPZRL
廠商： Analog Devices Inc
文件頁數(shù)： 32/32頁
文件大?。?/td> 0K
描述： IC ADC 14BIT DIFF 1MSPS 48LFCSP
標準包裝： 2,500
系列： PulSAR®
位數(shù)： 14
采樣率（每秒）： 1M
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 260mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應商設備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個差分，雙極
Data Sheet
AD7952
Rev. A | Page 9 of 32
Pin No.
Mnemonic
Type1
Description
11, 12
D[0:1] or
DI/O
In parallel mode, these outputs are used as Bit 0 and Bit 1 of the parallel port data output bus.
DIVSCLK[0:1]
Serial Data Division Clock Selection. In serial master read after convert mode (SER/PAR = high,
EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated serial
data clock that clocks the data output. In other serial modes, these pins are high impedance outputs.
13
D2 or
DI/O
In parallel mode, this output is used as Bit 2 of the parallel port data output bus.
EXT/INT
Serial Data Clock Source Select. In serial mode, this input is used to select the internally generated
(master) or external (slave) serial data clock for the AD7952 output data.
When EXT/INT = low (master mode), the internal serial data clock is selected on SDCLK output.
When EXT/INT = high (slave mode), the output data is synchronized to an external clock signal (gated
by CS) connected to the SDCLK input.
14
D3 or
DI/O
In parallel mode, this output is used as Bit 3 of the parallel port data output bus.
INVSYNC
Serial Data Invert Sync Select. In serial master mode (SER/PAR = high, EXT/INT = low), this input is
used to select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.
15
D4 or
DI/O
In parallel mode, this output is used as Bit 4 of the parallel port data output bus.
INVSCLK
In all serial modes, invert SDCLK/SCCLK select. This input is used to invert both SDCLK and SCCLK.
When INVSCLK = low, the rising edge of SDCLK/SCCLK are used.
When INVSCLK = high, the falling edge of SDCLK/SCCLK are used.
16
D5 or
DI/O
In parallel mode, this output is used as Bit 5 of the parallel port data output bus.
RDC or
Serial Data Read During Convert. In serial master mode (SER/PAR = high, EXT/INT = low), RDC is
used to select the read mode. Refer to the Master Serial Interface section.
When RDC = low, the current result is read after conversion. Note the maximum throughput is
not attainable in this mode.
When RDC = high, the previous conversion result is read during the current conversion.
SDIN
Serial Data In. In serial slave mode (SER/PAR = high, EXT/INT = high), SDIN can be used as a data input
to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data
level on SDIN is output on SDOUT with a delay of 16 SDCLK periods after the initiation of the read sequence.
17
OGND
P
Input/Output Interface Digital Power Ground. Ground reference point for digital outputs. Should
be connected to the system digital ground ideally at the same potential as AGND and DGND.
18
OVDD
P
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host
interface 2.5 V, 3 V, or 5 V and decoupled with 10 μF and 100 nF capacitors.
19
DVDD
P
Digital Power. Nominally at 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors. Can
be supplied from AVDD.
20
DGND
P
Digital Power Ground. Ground reference point for digital outputs. Should be connected to system
digital ground ideally at the same potential as AGND and OGND.
21
D6 or
DO
In parallel mode, this output is used as Bit 6 of the parallel port data output bus.
SDOUT
Serial Data Output. In all serial modes, this pin is used as the serial data output synchronized to SDCLK.
Conversion results are stored in an on-chip register. The AD7952 provides the conversion result,
MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C.
When EXT/INT = low (master mode), SDOUT is valid on both edges of SDCLK.
When EXT/INT = high (slave mode):
When INVSCLK = low, SDOUT is updated on SDCLK rising edge.
When INVSCLK = high, SDOUT is updated on SDCLK falling edge.
22
D7 or
DI/O
In parallel mode, this output is used as Bit 7 of the parallel port data output bus.
SDCLK
Serial Data Clock. In all serial modes, this pin is used as the serial data clock input or output,
dependent on the logic state of the EXT/INT pin. The active edge where the data SDOUT is
updated depends on the logic state of the INVSCLK pin.
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