參數(shù)資料
型號: AD7951BSTZRL
廠商: Analog Devices Inc
文件頁數(shù): 31/32頁
文件大?。?/td> 0K
描述: IC ADC 14BIT 1MSPS 48-LQFP
標(biāo)準(zhǔn)包裝: 2,000
系列: PulSAR®
位數(shù): 14
采樣率(每秒): 1M
數(shù)據(jù)接口: 串行,并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 260mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,雙極
AD7951
Data Sheet
Rev. A | Page 8 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
06
39
6-
0
04
P
DBUF
P
DRE
F
RE
F
BUF
IN
TE
M
P
AV
D
IN
+
AG
ND
VEE
VC
C
IN
RE
F
G
ND
RE
F
D2
/E
X
T
/I
NT
D3/
INV
S
Y
NC
D
4/IN
V
S
C
L
K
D5/
RDC/
S
D
IN
OG
N
D
OV
D
DV
DD
DG
ND
D6/
S
DO
UT
D7
/S
DCL
K
D8/
S
Y
N
C
D9/
RDE
RRO
R
AGND
AVDD
AGND
BYTESWAP
OB/2C
SER/PAR
NC
D0/DIVSCLK[0]
D1/DIVSCLK[1]
IMPULSE
WARP
BIPOLAR
CNVST
PD
RESET
CS
RD
TEN
BUSY
D13/SCCS
D12/SCCLK
D11/SCIN
D10/HW/SW
48 47 46 45 44 43 42 41 40 39 38 37
35
34
33
30
31
32
36
29
28
27
25
26
2
3
4
7
6
5
1
8
9
10
12
11
13 14 15 16 17 18 19 20 21 22 23 24
PIN 1
AD7951
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT.
2. FOR THE LEAD FRAME CHIP SCALE PACKAGE (LFCSP), THE EXPOSED
PAD SHOULD BE CONNECTED TO VEE. THIS CONNECTION IS NOT
REQUIRED TO MEET THE ELECTRICAL PERFORMANCES.
Figure 4. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1, 3, 42
AGND
P
Analog Power Ground Pins. Ground reference point for all analog I/O. All analog I/O should be
referenced to AGND and should be connected to the analog ground plane of the system. In addition,
the AGND, DGND, and OGND voltages should be at the same potential.
2, 44
AVDD
P
Analog Power Pins. Nominally 4.75 V to 5.25 V and decoupled with 10 μF and 100 nF capacitors.
4
BYTESWAP
DI
Parallel Mode Selection (8-Bit/14-Bit). When high, the LSB is output on D[15:8] and the MSB is output
on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].
5
OB/2C
DI2
Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary.
When low, the MSB is inverted resulting in a twos complement output from its internal shift register.
6
WARP
DI2
Conversion Mode Selection. Used in conjunction with the IMPULSE input per the following:
Conversion Mode
WARP
IMPULSE
Normal
Low
Impulse
Low
High
Warp
High
Low
Normal
High
See the Modes of Operation section for a more detailed description.
7
IMPULSE
DI2
Conversion Mode Selection. See the WARP pin description in the previous row of this table. See the
Modes of Operation section for a more detailed description.
8
SER/PAR
DI
Serial/Parallel Selection Input.
When SER/PAR = low, the parallel mode is selected.
When SER/PAR = high, the serial modes are selected. Some bits of the data bus are used as a serial port
and the remaining data bits are high impedance outputs.
9, 10
NC
DO
No Connect. Do not connect.
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