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參數(shù)資料
| 型號(hào)： | AD7948BRZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT MULT PARALL 20SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時(shí)間： | 600ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 25µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電流，單極；1 電流，雙極 |
| 采樣率（每秒）： | 1.7M |
AD7943/AD7945/AD7948
REV. B
–9–
AD7943 PIN FUNCTION DESCRIPTIONS
Pin Mnemonic
Description
IOUT1
DAC current output terminal 1.
IOUT2
DAC current output terminal 2. This should be connected to the AGND pin.
AGND
This pin connects to the back gates of the current steering switches. In normal operation, it should be connected
to the signal ground of the system. In biased single-supply operation it may be biased to some voltage between
0 V and the 1.23 V. See Figure 11 for more details.
STB1
This is the Strobe 1 input. Data is clocked into the input shift register on the rising edge of this signal.
STB3
must be high. STB2, STB4 must be low.
LD1, LD2
Active low inputs. When both of these are low, the DAC register is updated and the output will change to
reflect this.
SRI
Serial Data Input. Data on this line will be clocked into the input shift register on one of the Strobe inputs,
when they are enabled.
STB2
This is the Strobe 2 input. Data is clocked into the input shift register on the rising edge of this signal.
STB3 must be high. STB1, STB4 must be low.
STB3
This is the Strobe 3 input. Data is clocked into the input shift register on the falling edge of this signal. STB1,
STB2, STB4, must be low.
STB4
This is the Strobe 4 input. Data is clocked into the input shift register on the rising edge of this signal.
STB3
must be high. STB1, STB2 must be low.
DGND
Digital Ground.
CLR
Asynchronous CLR input. When this input is taken low, all 0s are loaded to the DAC latch.
VDD
Power supply input. This is nominally +5 V for Normal Mode Operation and +3.3 V to +5 V for Biased
Mode Operation.
VREF
DAC reference input.
RFB
DAC feedback resistor pin.
AD7945 PIN FUNCTION DESCRIPTIONS
Pin Mnemonic
Description
IOUT1
DAC current output terminal 1.
AGND
This pin connects to the back gates of the current steering switches. The DAC IOUT2 terminal is also connected
internally to this point.
DGND
Digital Ground.
DB11–DB0
Digital Data Inputs.
CS
Active Low, Chip Select Input.
WR
Active Low, Write Input.
VDD
Power supply input. This is nominally +5 V for Normal Mode Operation and +3.3 V to +5 V for Biased Mode
Operation.
VREF
DAC reference input.
RFB
DAC feedback resistor pin.
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