參數(shù)資料
型號(hào)： AD7940BRM
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 5/20頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT UNIPOLAR 8-MSOP
標(biāo)準(zhǔn)包裝： 50
位數(shù)： 14
采樣率（每秒）： 100k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 26.4mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 1 個(gè)單端，單極
配用： EVAL-AD7940CBZ-ND - BOARD EVALUATION AD7940
AD7940-DBRD-ND - BOARD EVAL FOR AD7940 STAMP SPI
AD7940
Rev. A | Page 13 of 20
MODES OF OPERATION
The mode of operation of the AD7940 is selected by controlling
the (logic) state of the CS signal during a conversion. There are
two possible modes of operation, normal and power-down. The
point at which CS is pulled high after the conversion has been
initiated will determine whether or not the AD7940 will enter
power-down mode. Similarly, if already in power-down, CS can
control whether the device will return to normal operation or
remain in power-down. These modes of operation are designed
to provide flexible power management options. These options
can optimize the power dissipation/throughput rate ratio for
differing application requirements.
NORMAL MODE
This mode provides the fastest throughput rate performance
because the user does not have to worry about the power-up
times with the AD7940 remaining fully powered all the time.
Figure 16 shows the general diagram of the operation of the
AD7940 in this mode.
The conversion is initiated on the falling edge of CS as
described in the Serial Interface section. To ensure that the part
remains fully powered up at all times, CS must remain low until
at least 10 SCLK falling edges have elapsed after the falling edge
of CS. If CS is brought high any time after the 10th SCLK falling
edge, but before the 16th SCLK falling edge, the part will
remain powered up, but the conversion will be terminated and
SDATA will go back into three-state. At least 16 serial clock
cycles are required to complete the conversion and access the
complete conversion result. CS may idle high until the next
conversion or may idle low until CS returns high sometime
prior to the next conversion, effectively idling CS low.
Once a data transfer is complete (SDATA has returned to three-
state), another conversion can be initiated after the quiet time,
tQUIET, has elapsed by bringing CS low again.
03305-0-009
1
12
16
1 LEADING ZERO + CONVERSION RESULT
CS
SCLK
SDATA
Figure 16. Normal Mode Operation
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