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參數(shù)資料
| 型號： | AD7940-DBRD |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7940 STAMP SPI |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 0 ~ Vdd |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 17mW @ 100kSPS & 5V |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7940 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD7940BRJZ-REEL7DKR-ND - IC ADC 14BIT 100KSPS SOT-23-6 AD7940BRJZ-REEL7CT-ND - IC ADC 14BIT 100KSPS SOT-23-6 AD7940BRJZ-REEL7TR-ND - IC ADC 14BIT 100KSPS SOT-23-6 AD7940BRM-ND - IC ADC 14BIT UNIPOLAR 8-MSOP AD7940BRM-REEL7TR-ND - IC ADC 14BIT UNIPOLAR 8-MSOP |
AD7940
Rev. A | Page 11 of 20
CIRCUIT INFORMATION
The AD7940 is a fast, low power, 14-bit, single-supply ADC.
The part can be operated from a 2.50 V to 5.5 V supply. When
operated at either 5 V or 3 V supply, the AD7940 is capable of
throughput rates of 100 kSPS when provided with a 2.5 MHz
clock.
The AD7940 provides the user with an on-chip track-and-hold
ADC and a serial interface housed in a tiny 6-lead SOT-23
package or in an 8-lead MSOP package, which offer the user
considerable space-saving advantages over alternative solutions.
The serial clock input accesses data from the part and also
provides the clock source for the successive approximation
ADC. The analog input range for the AD7940 is 0 V to VDD. An
external reference is not required for the ADC nor is there a
reference on-chip. The reference for the AD7940 is derived from
the power supply and thus gives the widest dynamic input range.
The AD7940 also features a power-down option to save power
between conversions. The power-down feature is implemented
across the standard serial interface as described in the Modes of
Operation section.
CONVERTER OPERATION
The AD7940 is a 14-bit, successive approximation ADC based
around a capacitive DAC. The AD7940 can convert analog
show simplified schematics of the ADC. The ADC comprises of
control logic, SAR, and a capacitive DAC. Figure 11 shows the
ADC during its acquisition phase. SW2 is closed and SW1 is in
Position A. The comparator is held in a balanced condition and
the sampling capacitor acquires the signal on the selected VIN
channel.
03305-0-004
CAPACITIVE
DAC
CONTROL
LOGIC
SAMPLING
CAPACITOR
COMPARATOR
ACQUISITION
PHASE
A
B
SW1
VDD/2
SW2
VIN
Figure 11. ADC Acquisition Phase
When the ADC starts a conversion, SW2 will open and SW1
will move to Position B, causing the comparator to become
unbalanced (Figure 12). The control logic and the capacitive
DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator back into
a balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code (see the ADC Transfer Function section).
03305-0-005
CAPACITIVE
DAC
CONTROL
LOGIC
SAMPLING
CAPACITOR
COMPARATOR
CONVERSION
PHASE
A
B
SW1
VDD/2
SW2
VIN
Figure 12. ADC Conversion Phase
ANALOG INPUT
Figure 13 shows an equivalent circuit of the analog input
structure of the AD7940. The two diodes, D1 and D2, provide
ESD protection for the analog inputs. Care must be taken to
ensure that the analog input signal never exceeds the supply
rails by more than 300 mV. This will cause these diodes to
become forward-biased and to start conducting current into the
substrate. The maximum current these diodes can conduct
without causing irreversible damage to the part is 10 mA.
Capacitor C1 in Figure 13 is typically about 5 pF and primarily
can be attributed to pin capacitance. Resistor R1 is a lumped
component made up of the on resistance of a switch (track-and-
hold switch). This resistor is typically about 25 . Capacitor C2
is the ADC sampling capacitor and has a capacitance of 25 pF
typically. For ac applications, removing high frequency
components from the analog input signal is recommended by
use of an RC low-pass filter on the relevant analog input pin. In
applications where harmonic distortion and signal-to-noise
ratio are critical, the analog input should be driven from a low
impedance source. Large source impedances will significantly
affect the ac performance of the ADC. This may necessitate the
use of an input buffer amplifier. The choice of the op amp will
be a function of the particular application. When no amplifier is
used to drive the analog input, the source impedance should be
limited to low values. The maximum source impedance will
depend on the amount of total harmonic distortion (THD) that
can be tolerated. The THD will increase as the source impedance
increases, and performance will degrade (see Figure 8).
03305-0-006
R1
C2
30pF
CONVERSION PHASE - SWITCH OPEN
TRACK PHASE - SWITCH CLOSED
VIN
VDD
C1
4pF
D1
D2
Figure 13. Equivalent Analog Input Circuit
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