參數(shù)資料
型號： AD7938
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 8-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer
中文描述： 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, QCC32
封裝： MO-220-VHHD, LFCSP-32
文件頁數(shù)： 17/32頁
文件大?。?/td> 1332K
代理商： AD7938
Preliminary Technical Data
AD7938/AD7939
Table 9. Analog Input Type Selection
Channel Address
MODE0 = 0, MODE1 = 0
Eight Single-Ended
I/P Channels
V
IN+
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
MODE0 = 0, MODE1 = 1
Four Fully Differential
I/P Channels
V
IN+
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
MODE0 = 1, MODE1 = 0
Four Pseudo-Differential I/P
Channels (Pseudo Mode 1)
V
IN+
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
MODE0 = 1, MODE1 = 1
Seven Pseudo-Differential I/P
Channels (Pseudo Mode 2)
V
IN+
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
Not Allowed
ADD2
0
0
0
0
1
1
1
1
ADD1
0
0
1
1
0
0
1
1
ADD0
0
1
0
1
0
1
0
1
V
IN-
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
V
IN-
VIN1
VIN0
VIN3
VIN2
VIN5
VIN4
VIN7
VIN6
V
IN-
VIN1
VIN0
VIN3
VIN2
VIN5
VIN4
VIN7
VIN6
V
IN-
VIN7
VIN7
VIN7
VIN7
VIN7
VIN7
VIN7
SEQUENCER OPERATION
The configuration of the SEQ and SHDW bits in the control register allows the user to select a particular mode of operation of the
sequencer function. T
outlines the four modes of operation of the sequencer.
able 10
Table 10. Sequence Selection
SEQ
SHDW
Sequence Type
This configuration is selected when the sequence function is not used. The analog input channel selected on each
individual conversion is determined by the contents of the channel address bits, ADD2 to ADD0, in each prior write
operation. This mode of operation reflects the traditional operation of a multichannel ADC, without the sequencer
function being used, where each write to the AD7938/AD7939 selects the next channel for conversion.
This configuration selects the shadow register for programming. The following write operation loads the data on DB0 to
DB7 to the shadow register. This will program the sequence of channels to be converted continuously after each CONVST
falling edge (see the shadow register description and Table 11).
If the SEQ and SHADOW bits are set in this way, the sequence function is not interrupted upon completion of the WRITE
operation. This allows other bits in the control register to be altered between conversions while in a sequence without
terminating the cycle.
1
1
This configuration is used in conjunction with the channel address bits (ADD2 to ADD0) to program continuous
conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel as determined by
the channel address bits in the control register.
Table 10
0
0
0
1
1
0
SHADOW REGISTER
The shadow register on the AD7938/AD7939 is an 8-bit, write-only register. Data is loaded from DB0 to DB7 on the rising edge of WR.
The eight LSBs load into the shadow register. The information is written into the shadow register provided that the SEQ and SHDW bits
in the control register were set to 0 and 1, respectively in the previous write to the control register. Each bit represents an analog input
from Channel 0 through Channel 7. A sequence of channels may be selected through which the AD7938/AD7939 cycles with each
consecutive conversion after the write to the shadow register. To select a sequence of channels to be converted, if operating in single-
ended mode or Pseudo Mode 2, the associated channel bit in the shadow register must be set for each required analog input. When
operating in differential mode or Pseudo Mode 1, the associated pair of channels’ bits must be set for each pair of analog inputs required
in the sequence. With each consecutive CONVST pulse after the sequencer has been set up, the AD7938/AD7939 progress through the
selected channels in ascending order, beginning with the lowest channel. This continues until a write operation occurs with the SEQ and
SHDW bits configured in any way except 1, 0 (see
). When a sequence is set up in differential or Pseudo Mode 1, the ADC does
not convert on the inverse pairs (i.e., VIN1, VIN0). The bit functions of the shadow register are outlined in
section for further information on using the sequencer.
Selection
. See the An
Table 11
Table 11. Shadow Register Bit Functions
V
IN
0
V
IN
1
alog Input
V
IN
2
V
IN
3
V
IN
4
V
IN
5
V
IN
6
V
IN
7
Rev. PrN | Page 17 of 32
相關(guān)PDF資料
PDF描述
AD7938BCP 8-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer
AD7938BSU 8-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer
AD7939 8-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer
AD7939BCP 8-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer
AD7939BSU 8-Channel, 1.5 MSPS, 12-Bit and 10-Bit Parallel ADCs with a Sequencer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7938-6 制造商:AD 制造商全稱:Analog Devices 功能描述:8-Channel, 625 kSPS, 12-Bit Parallel ADCs with a Sequencer
AD7938BCP 制造商:Analog Devices 功能描述:ADC Single SAR 1.5Msps 12-bit Parallel 32-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:12-BIT PARALLEL ITF MULTICHANNEL ADC I.C - Bulk
AD7938BCP-6 制造商:Analog Devices 功能描述:ADC Single SAR 625ksps 12-bit Parallel 32-Pin LFCSP EP
AD7938BCP-6REEL7 制造商:Analog Devices 功能描述:ADC Single SAR 625ksps 12-bit Parallel 32-Pin LFCSP EP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 625KSPS 12-BIT PARALLEL 32LFCSP EP - Tape and Reel
AD7938BCP-REEL 制造商:Analog Devices 功能描述:ADC Single SAR 1.5Msps 12-bit Parallel 32-Pin LFCSP EP T/R
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*