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參數(shù)資料
| 型號： | AD7877ACPZ-500RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Touch Screen Controller |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 30/44頁 |
| 文件大?。?/td> | 1002K |
| 代理商： | AD7877ACPZ-500RL7 |
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AD7877
GENERAL-PURPOSE I/O PINS
The AD7877 has one dedicated general-purpose logic input/
output pin (GPIO4), and any or all of the three auxiliary analog
inputs can also be reconfigured as GPIOs. Associated with the
GPIOs are two 8-bit control registers and one 8-bit data register,
which are accessed using the extended write mode.
Rev. A | Page 30 of 44
As mentioned previously, GPIO registers are written to using
the extended writing mode. The first four bits of the data-word
must be 1111b to access the extended writing map, and the next
four bits are the GPIO register address. This leaves 8 bits for the
GPIO register data, because all GPIO registers are 8 bits.
The GPIO control registers are located at Extended Writing
Map Addresses 0000b and 0001b, and the GPIO data register is
at Address 0010b. GPIO registers are read in the same way as
other registers, by writing a 5-bit address to Control Register 1.
The GPIO registers are located at Read Addresses 11011b to
11101b.
GPIO CONFIGURATION
Each GPIO pin is configured by four bits in one of the GPIO
control registers and has a data bit in the GPIO data register.
The GPIO configuration bits are described in the following
sections and in Table 12. Also see the Detailed Register
Descriptions section.
Enable—EN
These bits enable or disable the GPIO pins. When EN = 0, the
corresponding GPIO pin is configured as the alternate function
(AUX input). The other GPIO configuration bits have no effect,
if the particular GPIO is not enabled. When EN = 1, the pin is
configured as a GPIO pin. GPIO4, which does not have an
alternate function, does not have an EN bit; it is always enabled.
Direction—DIR
These bits set the direction of the GPIO pins. When DIR = 0,
the pin is an output. Setting or clearing the relevant bit in the
GPIO data register outputs a value on the corresponding GPIO
pin. The output value depends on the POL bit.
When DIR = 1, the pin is an input. An input value on the
relevant GPIO pin sets or clears the corresponding bit in the
GPIO data register, depending on the POL bit. A GPIO data
register bit is read-only when DIR = 1 for that GPIO.
Polarity—POL
When POL = 0, the GPIO pin is active low. When POL = 1, the
GPIO pin is active high. How this bit affects the GPIO opera-
tion also depends on the DIR bit.
If POL = 1 and DIR = 1, a 1 at the input pin sets the corre-
sponding GPIO data register bit to 1. A 0 at the input pin clears
the corresponding GPIO data bit to 0.
If POL = 1 and DIR = 0, a 1 in the GPIO data register bit puts a
1 on the corresponding GPIO output pin. A 0 in the GPIO data
register bit puts a 0 on the GPIO output pin.
If POL = 0 and DIR = 1, a 1 at the input pin sets the corre-
sponding GPIO data bit to 0. A 0 at the input pin clears the
corresponding GPIO data bit to 1.
If POL = 0 and DIR = 0, a 1 in the GPIO data register bit puts a
0 on the corresponding GPIO output pin. A 0 in the GPIO data
register bit puts a 1 on the GPIO output pin.
Alert Enable—ALEN
GPIOs can operate as interrupt sources to trigger the ALERT
output. This is controlled by the alert enable (ALEN) bits in the
GPIO configuration registers. When ALEN = 1, the correspond-
ing GPIO can trigger an ALERT. When ALEN = 0, the corre-
sponding GPIO cannot cause the ALERT output to assert.
ALERT is asserted low, if any GPIO data register bit is set when
the GPIO is configured as an input. The GPIO data bit is set, if a
1 appears on the GPIO input pin when POL = 1, or if a 0
appears on the GPIO input pin when POL = 0. Note that
ALERT is triggered only when the GPIO is configured as an
input, that is, when DIR = 1. ALERT can never be triggered by a
GPIO that is configured as an output, that is, DIR = 0.
ALERT Output
The ALERT pin is an alarm or interrupt output that goes low, if
any one of a number of interrupt sources is asserted. The results
of high and low limit comparisons on the AUX1, BAT1, BAT2,
and TEMP1 channels are interrupt sources. An out-of-limit
comparison sets a status bit in the alert status/mask register
(Address 00011b).There are separate status bits for both the
high and low limits on each channel to indicate which limit was
exceeded. The interrupt sources can be masked out by clearing
the corresponding enable bit in this register. There is one enable
bit per channel.
ALERT is also asserted, if an input on a GPIO pin sets a bit in
the GPIO data register, as explained in the previous section.
GPIO interrupts can be disabled by clearing the corresponding
ALEN bit in the GPIO control registers.
The interrupt source can be identified by reading the GPIO data
register and the alert status/enable register. ALERT remains
asserted until the source of the interrupt has been masked out
or removed.
If the ALERT source is a GPIO, then masking out the interrupt
by clearing the corresponding ALEN bit to 0 or removing the
source of the interrupt on the GPIO pin causes ALERT to go
high again.
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