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參數(shù)資料
| 型號： | AD7874AQ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS 12BIT 4CH 5V 28-CDIP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS） |
| 分辨率（位）： | 12 b |
| 采樣率（每秒）： | 116k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 電壓電源： | 雙 ± |
| 電源電壓： | ±5V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 28-CDIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 28-CDIP |
| 包裝： | 管件 |
AD7874
REV. C
–10–
MICROPROCESSOR INTERFACING
The AD7874 high speed bus timing allows direct interfacing to
DSP processors as well as modern 16-bit microprocessors.
Suitable microprocessor interfaces are shown in Figures 12
through 16.
AD7874–ADSP-2100 Interface
Figure 12 shows an interface between the AD7874 and the
ADSP-2100. Conversion is initiated using a timer which allows
very accurate control of the sampling instant on all four chan-
nels. The AD7874 INT line provides an interrupt to the ADSP-
2100 when conversion is completed on all four channels. The
four conversion results can then be read from the AD7874 using
four successive reads to the same memory address. The follow-
ing instruction reads one of the four results (this instruction is
repeated four times to read all four results in sequence):
MR0 = DM(ADC)
where MR0 is the ADSP-2100 MR0 register and
ADC is the AD7874 address.
TIMER
DMA0
DMA13
DMD15
DMD0
DMS
EN
ADDR
DECODE
ADDRESS BUS
ADSP-2100
(ADSP-2101/
ADSP-2102)
* ADDITIONAL PINS OMITTED FOR CLARITY
DATA BUS
CONVST
CS
DB11
DB0
RD
INT
AD7874*
IRQn
DMRD (RD)
Figure 12. AD7874–ADSP-2100 Interface
AD7874–ADSP-2101/ADSP-2102 Interface
The interface outlined in Figure 12 also forms the basis for an
interface between the AD7874 and the ADSP-2101/ADSP-2102.
The READ line of the ADSP-2101/ADSP-2102 is labeled RD.
In this interface, the RD pulse width of the processor can be
programmed using the Data Memory Wait State Control Regis-
ter. The instruction used to read one of the four results is as
outlined for the ADSP-2100.
AD7874–TMS32010 Interface
An interface between the AD7874 and the TMS32010 is shown
in Figure 13. Once again the conversion is initiated using an ex-
ternal timer and the TMS32010 is interrupted when all four
conversions have been completed. The following instruction is
used to read the conversion results from the AD7874:
IN D,ADC
where D is Data Memory address and
ADC is the AD7874 address.
PA0
PA2
D15
D0
MEN
EN
ADDR
DECODE
ADDRESS BUS
TIMER
DATA BUS
CONVST
CS
DB11
DB0
RD
INT
AD7874*
TMS32010
*ADDITIONAL PINS OMITTED FOR CLARITY
INT
DEN
Figure 13. AD7874–TMS32010 Interface
AD7874–TMS320C25 Interface
Figure 14 shows an interface between the AD7874 and the
TMS320C25. As with the two previous interfaces, conversion is
initiated with a timer and the processor is interrupted when the
conversion sequence is completed. The TMS320C25 does not
have a separate RD output to drive the AD7874 RD input di-
rectly. This has to be generated from the processor STRB and
R/W outputs with the addition of some logic gates. The RD sig-
nal is OR-gated with the MSC signal to provide the one WAIT
state required in the read cycle for correct interface timing.
Conversion results are read from the AD7874 using the follow-
ing instruction:
IN D,ADC
where D is Data Memory address and
ADC is the AD7874 address.
A0
A15
D15
D0
IS
EN
ADDR
DECODE
ADDRESS BUS
TIMER
DATA BUS
CONVST
CS
DB11
DB0
RD
INT
AD7874*
TMS320C25
*ADDITIONAL PINS OMITTED FOR CLARITY
INTn
R/W
STRB
MSC
READY
Figure 14. AD7874–TMS320C25 Interface
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