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參數資料
| 型號： | AD7868AR |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 15/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O PORT 12BIT ANLG 28-SOIC |
| 產品變化通告： | AD7868 Discontinuation 05/Sept/2011 |
| 標準包裝： | 1 |
| 應用： | 模擬 I/O |
| 接口： | TTL/CMOS |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC W |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
AD7868
–8–
REV. B
TIMING AND CONTROL
Communication with the AD7868 is managed by 6 dedicated
pins. These consist of separate serial clocks, word framing or
strobe pulses and data signals for both receiving and transmit-
ting data. Conversion starts and DAC updating are controlled
by two digital inputs; CONVST and LDAC. These inputs can
be asserted independently of the microprocessor by an external
timer when precise sampling intervals are required. Alterna-
tively, the LDAC and CONVST can be driven from a decoded
address bus allowing the microprocessor control over conversion
start and DAC updating as well as data communication to the
AD7868.
ADC Timing
Conversion control is provided by the CONVST input. A low to
high transition on CONVST input starts conversion and drives
the track/hold amplifier into its hold mode. Serial data then be-
comes available while conversion is in progress. The correspond-
ing timing diagram is shown in Figure 7. The word length is 16
bits; 4 leading zeros, followed by the 12-bit conversion result
starting with the MSB. The data is synchronized to the serial
clock output (RCLK) and is framed by the serial strobe (RFS).
Data is clocked out on a low to high transition of the serial clock
and is valid on the falling edge of this clock while the RFS out-
put is low. RFS goes low at the start of conversion and the first
serial data bit (which is the first leading zero) is valid on the first
falling edge of RCLK. All the ADC serial lines are open-drain
outputs and require external pull-up resistors.
The serial clock out is derived from the ADC master clock
source which may be internal or external. Normally, RCLK is
required during the serial transmission only. In these cases it can
be shut down (i.e., placed into high impedance) at the end of
conversion to allow multiple ADCs to share a common serial
bus. However, some serial systems (e.g., TMS32020) require a
serial clock which runs continuously. Both options are available
on the AD7868 ADC. With the CONTROL input at 0 V, RCLK
is noncontinuous and when it is at –5 V, RCLK is continuous.
DAC Timing
The AD7868 DAC contains two latches, an input latch and a
DAC latch. Data must be loaded to the input latch under the
control of the TCLK, TFS and DT serial logic inputs. Data is
then transferred from the input latch to the DAC latch under
the control of the LDAC signal. Only the data in the DAC latch
determines the analog output of the AD7868.
Data is loaded to the input latch under control of TCLK, TFS
and DT. The AD7868 DAC expects a 16-bit stream of serial
data on its DT input. Data must be valid on the falling edge of
TCLK. The TFS input provides the frame synchronization sig-
nal which tells the AD7868 DAC that valid serial data will be
available for the next 16 falling edges of TCLK. Figure 8 shows
the timing diagram for the serial data format.
Although 16 bits of data are clocked into the input latch, only
12 bits are transferred into the DAC latch. Therefore, 4 bits in
the stream are don’t cares since their value does not affect the
DAC latch data. The bit positions are 4 don’t cares followed by
the 12-bit DAC data starting with the MSB.
The LDAC signal controls the transfer of data to the DAC
latch. Normally, data is loaded to the DAC latch on the falling
edge of LDAC. However, if LDAC is held low, then serial data
is loaded to the DAC latch on the sixteenth falling edge of
TCLK. If LDAC goes low during the loading of serial data to
the input latch, no DAC latch update takes place on the falling
edge of LDAC. If LDAC stays low until the serial transfer is
completed, then the update takes place on the sixteenth falling
edge of TCLK. If LDAC returns high before the serial data
transfer is completed, no DAC latch update takes place.
NOTES
1EXTERNAL 4.7k
PULL-UP RESISTOR
2EXTERNAL 2k
PULL-UP RESISTOR
3CONTINUOUS RCLK (DASHED LINE) WHEN THE CONTROL INPUT = –5V AND
NONCONTINUOUS WHEN THE CONTROL INPUT = 0V
t13
t3
CONVST
RFS
1
RCLK
2, 3
DR
1
DB11
DB10
DB9
DB1
DB0
CONVERSION TIME
t1
t5
t2
t4
t6
Figure 7. ADC Control Timing Diagram
DB11
DB10
DB1
DB0
t7
t8
t9
t10
t11
TFS
TCLK
DT
DON'T
CARE
DON'T
CARE
DON'T
CARE
DON'T
CARE
Figure 8. DAC Control Timing Diagram
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| AD7868AR-REEL | 功能描述:IC I/O PORT 12BIT ANLG 28-SOIC RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| AD7868ARZ | 功能描述:IC I/O PORT 12BIT ANLG 28-SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| AD7868ARZ-REEL | 功能描述:IC I/O PORT 12BIT ANLG 28-SOIC RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| AD7868BN | 制造商:Analog Devices 功能描述:Data Acquisition System Single ADC Single DAC 12-Bit 24-Pin PDIP 制造商:Analog Devices 功能描述:ANALOG I/O PORT IC - Rail/Tube 制造商:Rochester Electronics LLC 功能描述:ANALOG I/O PORT IC - Bulk |
| AD7868BNZ | 功能描述:IC I/O PORT 12BIT ANLG 24-DIP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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