Limit at TMIN, TMAX Parameter (A, B Ver" />
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  • 參數(shù)資料
    型號(hào): AD7868AR-REEL
    廠商: Analog Devices Inc
    文件頁(yè)數(shù): 11/16頁(yè)
    文件大?。?/td> 0K
    描述: IC I/O PORT 12BIT ANLG 28-SOIC
    產(chǎn)品變化通告: AD7868 Discontinuation 05/Sept/2011
    標(biāo)準(zhǔn)包裝: 1,000
    應(yīng)用: 模擬 I/O
    接口: TTL/CMOS
    電源電壓: 4.75 V ~ 5.25 V
    封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
    供應(yīng)商設(shè)備封裝: 28-SOIC W
    包裝: 帶卷 (TR)
    安裝類型: 表面貼裝
    AD7868
    –4–
    REV. B
    Limit at TMIN, TMAX
    Parameter
    (A, B Versions)
    (T Version)
    Units
    Conditions/Comments
    ADC TIMING
    t1
    50
    ns min
    CONVST
    Pulse Width
    t2
    3
    440
    ns min
    RCLK Cycle Time, Internal Clock
    t3
    100
    ns min
    RFS
    to RCLK Falling Edge Setup Time
    t4
    20
    ns min
    RCLK Rising Edge to RFS
    100
    ns max
    t5
    4
    155
    ns max
    RCLK to Valid Data Delay, CL = 35 pF
    t6
    4
    ns min
    Bus Relinquish Time after RCLK
    100
    ns max
    t13
    5
    2 RCLK +200 to
    ns typ
    CONVST
    to RFS Delay
    3 RCLK + 200
    DAC TIMING
    t7
    50
    ns min
    TFS
    to TCLK Falling Edge
    t8
    75
    100
    ns min
    TCLK Falling Edge to TFS
    t9
    6
    150
    200
    ns min
    TCLK Cycle Time
    t10
    30
    40
    ns min
    Data Valid to TCLK Setup Time
    t11
    75
    100
    ns min
    Data Valid to TCLK Hold Time
    t12
    40
    ns min
    LDAC
    Pulse Width
    NOTES
    1Timing specifications are sample tested at +25
    °C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a
    voltage level of 1.6 V.
    2Serial timing is measured with a 4.7 k
    pull-up resistor on DR and RFS and a 2 k pull-up resistor on RCLK . The capacitance on all three output is 35 pF.
    3When using internal clock, RCLK mark/space ratio (measured from a voltage level of 1.6 V) range is 40/60 to 60/40. For external clock, RCLK mark/space ratio =
    external clock mark/space ratio.
    4DR will drive higher capacitance loads but this will add to t
    5 since it increases the external RC time constant (4.7 k /CL) and hence the time to reach 2.4 V.
    5Time 2 RCLK to 3 RCLK depends on conversion start to ADC clock synchronization.
    6TCLK mark/space ratio is 40/60 to 60/40.
    TIMING CHARACTERISTICS1, 2
    WARNING!
    ESD SENSITIVE DEVICE
    CAUTION
    ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
    accumulate on the human body and test equipment and can discharge without detection.
    Although the AD7868 features proprietary ESD protection circuitry, permanent damage may
    occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
    precautions are recommended to avoid performance degradation or loss of functionality.
    ABSOLUTE MAXIMUM RATINGS*
    (TA = +25°C unless otherwise noted)
    VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
    VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
    AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V
    VOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD
    VIN to AGND . . . . . . . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V
    RO ADC to AGND . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
    RO DAC to AGND . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
    RI DAC to AGND . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
    Digital Inputs to AGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
    Digital Outputs to AGND . . . . . . . . . . –0.3 V to VDD + 0.3 V
    Operating Temperature Range
    A, B Versions . . . . . . . . . . . . . . . . . . . . . . . –40
    °C to +85°C
    T Version . . . . . . . . . . . . . . . . . . . . . . . . . –55
    °C to +125°C
    Storage Temperature Range . . . . . . . . . . . . –65
    °C to +150°C
    Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300
    °C
    Power Dissipation (Any Package) to +75
    °C . . . . . . . . 450 mW
    Derates above +75
    °C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
    *Stresses above those listed under “Absolute Maximum Ratings” may cause
    permanent damage to the device. This is a stress rating only and functional
    operation of the device at these or any other conditions above those listed in the
    operational sections of this specification is not implied. Exposure to absolute
    maximum rating conditions for extended periods may affect device reliability.
    DIP
    RO ADC
    DGND
    TCLK
    DT
    RI DAC
    AGND
    CONTROL
    CLK
    RCLK
    DR
    DGND
    AGND
    RO DAC
    NC
    VDD
    NC = NO CONNECT
    24
    23
    22
    21
    20
    19
    18
    17
    16
    15
    14
    13
    1
    2
    3
    4
    5
    6
    7
    8
    10
    11
    12
    9
    AD7868
    TOP VIEW
    (Not to Scale)
    CONVST
    RFS
    VSS
    VOUT
    VIN
    TFS
    LDAC
    VDD
    VSS
    SOIC
    RO ADC
    DGND
    TCLK
    DT
    RI DAC
    AGND
    CONTROL
    CLK
    RCLK
    DR
    DGND
    AGND
    RO DAC
    NC
    VDD
    NC = NO CONNECT
    1
    7
    8
    9
    24
    23
    22
    21
    20
    19
    18
    17
    16
    15
    14
    12
    13
    AD7868
    TOP VIEW
    (Not to Scale)
    CONVST
    RFS
    VSS
    VOUT
    VIN
    TFS
    LDAC
    10
    11
    3
    4
    5
    6
    2
    28
    27
    26
    25
    NC
    VDD
    VSS
    PIN CONFIGURATIONS
    (VDD = +5 V
    5%, VSS = –5 V
    5%, AGND = DGND = 0 V)
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