參數(shù)資料
型號(hào): AD7865
廠商: Analog Devices, Inc.
英文描述: Simultaneous Sampling, Fast, 14-Bit ADC(四通道,同時(shí)采樣,高速,14位A/D轉(zhuǎn)換器)
中文描述: 同步采樣,快速,14位ADC(四通道,同時(shí)采樣,高速,14位的A / D轉(zhuǎn)換器)
文件頁(yè)數(shù): 7/21頁(yè)
文件大?。?/td> 375K
代理商: AD7865
AD7865
Rev. PrC
–7–
Preliminary Technical Data
PRELMNARY
Digital Ground. Ground reference for Digital circuitry. This DGND pin should be
connected to the system's AGND
plane at the AGND pin.
TECHNCAL
3V±10% supply to facilitate interfacing to 3V processors and DSPs.
12
AGND
Analog Ground. General analog ground. This AGND pin should be connected to the
system's AGND
plane.
13-16
V
IN4X
, V
IN3X
Analog Inputs. See Analog Input Section.
17
AGND
Analog Ground. Analog Ground reference for the attenuator circuitry. This
AGND pin should be connected to the system's AGND
plane.
18-21
V
IN2X
, V
IN1X
Analog Inputs. See Analog Input Section.
22
STBY
Standby Mode Input. TTL-compatible input which is used to put the device into the
power save or standby mode. The
STBY
input is high for normal operation and low
for standby operation.
23
V
REF
AGND
Reference Ground. Ground reference for the part's on-chip reference buffer. The
V
REF
AGND pin should be connected to the system's AGND
plane.
24
V
REF
20mV) and also allows the internal reference to be overdriven by an external refer-
ence source (2.5V ± 5%) . A 0.1μF decoupling capacitor should be connected
between this pin and AGND.
25
AV
DD
Analog Positive Supply Voltage, +5.0 V ±5%.
26
AGND
Analog Ground. Analog Ground reference for the DAC circuitry.
27 - 34
DB13- DB6
Data Bit 13 is the MSB, followed by Data Bit 12 to Data Bit 6. Three-state TTL
outputs. Output coding is 2's complement.
35
DV
DD
Positive Supply Voltage for Digital section, +5.0V ±5%. A 0.1μF decoupling
capacitor should be connected between this pin and AGND. Both DV
DD
and AV
DD
should be externally tied together.
36
V
DRIVE
This pin provides the positive supply voltage for the output drivers (DB0 to DB11),
BUSY,
EOC
and FRSTDATA. It is normally tied to DV
DD
. V
DRIVE
should be
decoupled with a 0.1μF capacitor. It allows improved performance when reading
during the conversion sequence. Also, the output data drivers may be powered by a
37
DGND
38, 39
DB5, DB4
Data Bit 5 to Data Bit 4. Three-state TTL outputs.
40 - 43
DB3 - DB0
Data Bit 3 to Data Bit 0. Bidirectional data pins. When a read operation takes place,
these pins are Three-state TTL outputs. The channel select register is programmed
with the data on the DB0 - DB3 pins with standard
CS
and
WR
signals. DB0
represents channel 1 and DB3 represents channel 4.
44
EOC
End-of-Conversion. Active low logic output indicating conversion status. The end
of each conversion in a conversion sequence is indicated by a low-going pulse on this
line.
相關(guān)PDF資料
PDF描述
AD7868 Complete 12-bit I/O System Containing a DAC And an ADC(完備的12位I\O系統(tǒng)(包含一個(gè)A/D轉(zhuǎn)換器和一個(gè)D/A轉(zhuǎn)換器))
AD7869 Complete 14-bit I/O System Containing a DAC and a ADC(完備的14位I/O系統(tǒng)(包含一個(gè)A/D轉(zhuǎn)換器和一個(gè)D/A轉(zhuǎn)換器))
AD7870AJN LC2MOS Complete, 12-Bit, 100 kHz , Sampling ADC
AD7874AN LC2MOS 4-Channel, 12-Bit Simultaneous Sampling Data Acquisition System
AD7874AQ LC2MOS 4-Channel, 12-Bit Simultaneous Sampling Data Acquisition System
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