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參數(shù)資料
| 型號： | AD7864 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Four Channel, Simultaneous Sampling, High Speed, 12-Bit ADC(四通道,同時采樣高速12位A/D轉(zhuǎn)換器) |
| 中文描述： | 四通道，同步采樣，高速，12位ADC（四通道，同時采樣高速12位的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 394K |
| 代理商： | AD7864 |
AD7864
–14–
REV. 0
low. At this point the logic output FRSTDATA will go logic
high to indicate that the output data register pointer is address-
ing Register Number 1. When
CS
and
RD
are both logic low
the contents of the addressed register are enabled onto the data
bus (DB0–DB11).
When reading the output data registers after a conversion
sequence, i.e., when BUSY goes low, the register pointer is
incremented on the rising edge of the
RD
signal as shown in
Figure 12. However, when reading the conversion results during
the conversion sequence the pointer will not be incremented
until a valid conversion result is in the register to be addressed.
In this case the pointer is incremented when the conversion has
ended and the result has been transferred to the output data
register. This happens just prior to
EOC
going low, therefore
EOC
may be used to enable the register contents onto the data
bus as described in Reading During the Conversion Sequence.
The pointer is reset to point to Register 1 on the rising edge of
the
RD
signal when the last conversion result in the sequence is
being read. In the example shown this means the pointer is set
to Register 1 when the contents of Register 3 are read.
DB0 TO DB11
O/P
DRIVERS
OE #1
NOT VALID
(V
IN3
)
(V
IN1
)
(V
IN4
)
OE #2
OE #3
OE #4
2-BIT
COUNTER
V
DRIVE
OE
RD
CS
RESET
D
OUTPUT DATA REGISTERS
*THE POINTER WILL NOT BE INCREMENTED BY A RISING EDGE ON
RD
UNTIL
THE CONVERSION RESULT IS IN THE OUTPUT DATA REGISTER. THE POINTER
IS RESET WHEN THE LAST CONVERSION RESULT IS READ
FRSTDATA
POINTER*
AD7864
Figure 12. Output Data Registers
OFFSET AND FULL-SCALE ADJUSTMENT
In most Digital Signal Processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale error effect is linear and does not cause
problems as long as the input signal is within the full dynamic
range of the ADC. Invariably, some applications will require
that the input signal span the full analog input dynamic range.
In such applications, offset and full-scale error will have to be
adjusted to zero.
Figure 13 shows a circuit which can be used to adjust the offset
and full-scale errors on the AD7864 (V
A1
on the AD7864-1
version is shown for example purposes only). Where adjustment
is required, offset error must be adjusted before full-scale error.
This is achieved by trimming the offset of the op amp driving
the analog input of the AD7864 while the input voltage is a
1/2 LSB below analog ground. The trim procedure is as follows:
apply a voltage of –2.44 mV (–1/2 LSB) at V
A1
in Figure 8 and
adjust the op amp offset voltage until the ADC output code
flickers between 1111 1111 1111 and 0000 0000 0000.
Gain error can be adjusted at either the first code transition
(ADC negative full scale) or the last code transition (ADC posi-
tive full scale). The trim procedures for both cases are as follows.
Positive Full-Scale Adjust
Apply a voltage of +9.9927 V (FS/2 – 3/2 LSBs) at V
A1
. Adjust
R2 until the ADC output code flickers between 0111 1111
1110 and 0111 1111 1111.
Negative Full-Scale Adjust
Apply a voltage of –9.9976 V (–FS + 1/2 LSB) at V
A1
and ad-
just R2 until the ADC output code flickers between 1000 0000
0000 and 1000 0000 0001.
An alternative scheme for adjusting full-scale error in systems
which use an external reference is to adjust the voltage at the
VREF pin until the full-scale error for any of the channels is
adjusted out. The good full-scale matching of the channels will
ensure small full-scale errors on the other channels.
V
1
R1
10k
V
R2
500
V
R3
10k
V
AGND
AD7864*
*ADDITIONAL PINS OMITTED FOR CLARITY
INPUT
RANGE =
6
10V
10k
V
R5
10k
V
R4
V
INXA
Figure 13. Full-Scale Adjust Circuit
DYNAMIC SPECIFICATIONS
The AD7864 is specified and 100% tested for dynamic perfor-
mance specifications as well as traditional dc specifications such
as integral and differential nonlinearity. These ac specifications
are required for the signal processing applications such as
phased array sonar, adaptive filters and spectrum analysis.
These applications require information on the ADC’s effect on
the spectral content of the input signal. Hence, the parameters
for which the AD7864 is specified include SNR, harmonic distor-
tion, intermodulation distortion and peak harmonics. These terms
are discussed in more detail in the following sections.
Signal-to-Noise Ratio (SNR)
SNR is the measured signal to noise ratio at the output of the
ADC. The signal is the rms magnitude of the fundamental.
Noise is the rms sum of all the nonfundamental signals up to
half the sampling frequency (f
S
/2) excluding dc. SNR is depen-
dent upon the number of quantization levels used in the digiti-
zation process; the more levels, the smaller the quantization
noise. The theoretical signal to noise ratio for a sine wave input
is given by
SNR
= (6.02
N
+ 1.76)
dB
where
N
is the number of bits.
Thus for an ideal 12-bit converter, SNR = 74 dB.
Figure 14 shows a histogram plot for 8192 conversions of a dc
input using the AD7864 with 5 V supply. The analog input was
set at the center of a code. It can be seen that all the codes
appear in the one output bin indicating very good noise perfor-
mance from the ADC.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD7864_09 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, Simultaneous Sampling, High Speed, 12-Bit ADC |
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| AD7864AS-1 | 制造商:Analog Devices 功能描述: 制造商:Analog Devices 功能描述:IC 12BIT ADC SMD 7864 LQFP44 |
| AD7864AS-2 | 制造商:Analog Devices 功能描述:ADC Single SAR 520ksps 12-bit Parallel 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:4 CH.SIMULTANEOUS SAMPL.500 KSPS ADC I.C - Bulk 制造商:Analog Devices 功能描述:IC 12-BIT ADC |
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