參數(shù)資料
型號(hào)： AD7863ARSZ-10
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 3/24頁(yè)
文件大小： 0K
描述： IC ADC 14BIT DUAL 2CHAN 28SSOP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 175k
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 94.5mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 管件
輸入數(shù)目和類型： 4 個(gè)單端，單極；4 個(gè)單端，雙極
AD7863
Rev. B | Page 11 of 24
Gain error can be adjusted at either the first code transition (ADC
negative full scale) or the last code transition (ADC positive full
scale). The trim procedures for both cases are as follows:
Positive Full-Scale Adjust (10 Version)
Apply a voltage of 9.9927 V (FS/2 – 1 LSBs) at V1. Adjust R2
until the ADC output code flickers between 01 1111 1111 1110
and 01 1111 1111 1111.
Negative Full-Scale Adjust (10 Version)
Apply a voltage of 9.9976 V (FS + 1 LSB) at V1. Adjust R2
until the ADC output code flickers between 10 0000 0000 0000
and 10 0000 0000 0001.
An alternative scheme for adjusting full-scale error in systems
that use an external reference is to adjust the voltage at the VREF
pin until the full-scale error for any of the channels is adjusted
out. The good full-scale matching of the channels ensures small
full-scale errors on the other channels.
TIMING AND CONTROL
Figure 7 shows the timing and control sequence required to
obtain optimum performance (Mode 1) from the AD7863. In
the sequence shown, a conversion is initiated on the falling edge
of CONVST. This places both track-and-holds into hold
simultaneously and new data from this conversion is available
in the output register of the AD7863 5.2 μs later. The BUSY
signal indicates the end of conversion and at this time the
conversion results for both channels are available to be read. A
second conversion is then initiated. If the multiplexer select (A0)
is low, the first and second read pulses after the first conversion
accesses the result from Channel A (VA1 and VA2, respectively).
The third and fourth read pulses, after the second conversion
and A0 high, accesses the result from Channel B (VB1 and VB2,
respectively). The state of A0 can be changed any time after the
CONVST goes high, that is, track-and-holds into hold and 500 ns
prior to the next falling edge of CONVST. Note that A0 should
not be changed during conversion if the nonselected channels
have negative voltages applied to them, which are outside the
input range of the AD7863, because this affects the conversion
in progress. Data is read from the part via a 14-bit parallel data
bus with standard CS and RD signal, that is, the read operation
consists of a negative going pulse on the CS pin combined with
two negative going pulses on the RD pin (while the CS is low),
accessing the two 14-bit results. Once the read operation has
taken place, a further 400 ns should be allowed before the next
falling edge of CONVST to optimize the settling of the track-
and-hold amplifier before the next conversion is initiated.
The achievable throughput rate for the part is 5.2 μs (conversion
time) plus 100 ns (read time) plus 0.4 μs (quiet time). This
results in a minimum throughput time of 5.7 μs (equivalent to
a throughput rate of 175 kHz).
VA1
VA2
VB1
VB2
CONVST
BUSY
A0
CS
RD
DATA
tCONV = 5.2s
06
41
1-
0
07
t3
t8
tACQ
t1
t4
t2
t5
t6
t7
Figure 7. Mode 1 Timing Operation Diagram for High Sampling Performance
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