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參數(shù)資料
| 型號： | AD7856KR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 5 V Single Supply, 8-Channel 14-Bit 285 kSPS Sampling ADC |
| 中文描述： | 8-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數(shù)： | 23/32頁 |
| 文件大?。?/td> | 294K |
| 代理商： | AD7856KR |
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AD7856
–23–
REV. A
required to reduced the offset and gain errors to at least the 14-
bit level. There will never be any need to perform more than
three system (offset + gain) calibrations.
The zero scale error is adjusted for an offset calibration and the
positive full-scale error is adjusted for a gain calibration.
System Calibration Timing
The calibration timing diagram in Figure 29 is for a full system
calibration where the falling edge of
CAL
initiates an internal
reset before starting a calibration (
note that if the part is in power-
down mode, the
CAL
pulsewidth must take account of the power-up
time
). For software calibrations with power-down modes, see
note in Power-Up Times section. If a full system calibration is
to be performed in software it is easier to perform separate gain
and offset calibrations so that the CONVST bit in the control
register does not have to be programmed in the middle of the
system calibration sequence. The rising edge of
CAL
starts
calibration of the internal DAC and causes the BUSY line to go
high. If the control register is set for a full system calibration,
the
CONVST
must be used also. The full-scale system voltage
should be applied to the analog input pins from the start of
calibration. The BUSY line will go low once the DAC and Sys-
tem Gain Calibration are complete. Next the system offset volt-
age is applied to the AIN pin for a minimum setup time (t
SETUP
)
of 100 ns before the rising edge of the
CONVST
and remains
until the BUSY signal goes low. The rising edge of the
CONVST
starts the system offset calibration section of the full system
calibration and also causes the BUSY signal to go high. The
BUSY signal will go low after a time t
CAL2
when the calibration
sequence is complete. In some applications not all the input
channels may be used. In this case it may be useful to dedicate
two input channels for the system calibration, one which has the
system offset voltage applied to it, and one which has the system
full scale voltage applied to it. When a system offset or gain
calibration is performed, the channel selected should correspond
to the system offset or system full-scale voltage channel.
The timing for a system (gain + offset) calibration is very similar
to that of Figure 29 the only difference being that the time t
CAL1
will be replaced by a shorter time of the order of t
CAL2
as the
internal DAC will not be calibrated. The BUSY signal will
signify when the gain calibration is finished and when the part is
ready for the offset calibration.
CONVST
(I/P)
AIN (I/P)
t
16
t
SETUP
CAL
(I/P)
BUSY (O/P)
t
1
t
15
t
1
= 100ns MIN,
t
16
= 2.5
t
CLKIN
MAX,
t
15
= 2.5
t
CLKIN
MAX,
t
CAL1
= 222228
t
CLKIN
MAX,
t
CAL2
= 27798
t
CLKIN
t
CAL1
t
CAL2
V
SYSTEM FULL SCALE
V
OFFSET
Figure 29. Timing Diagram for Full System Calibration
The timing diagram for a system offset or system gain calibra-
tion is shown in Figure 30. Here again the
CAL
is pulsed and
the rising edge of the
CAL
initiates the calibration sequence (or
the calibration can be initiated in software by writing to the
control register). The rising edge of the
CAL
causes the BUSY
line to go high and it will stay high until the calibration sequence is
finished. The analog input should be set at the correct level for a
minimum setup time (t
SETUP
) of 100 ns before the rising edge of
CAL
and stay at the correct level until the BUSY signal goes low.
AIN (I/P)
t
SETUP
BUSY (O/P)
t
15
t
1
V
SYSTEM FULL SCALE
OR V
SYSTEM OFFSET
CAL
(I/P)
t
CAL2
Figure 30. Timing Diagram for System Gain or System
Offset Calibration
SERIAL INTERFACE SUMMARY
Table IX details the two interface modes and the serial clock
edges from which the data is clocked out by the AD7856
(DOUT Edge) and that the data is latched in on (DIN Edge).
In both interface Modes 1, and 2 the
SYNC
is gated with the
SCLK. Thus the falling edge of
SYNC
may clock out the MSB
of data. Subsequent bits will be clocked out by the Serial Clock,
SCLK. The condition for the falling edge of
SYNC
clocking out
the MSB of data is as follows:
The falling edge of
SYNC
will clock out the MSB if the serial clock
is low when the
SYNC
goes low.
If this condition is not the case, the SCLK will clock out the
MSB. If a noncontinuous SCLK is used, it should idle high.
Table IX. SCLK Active Edges
Interface Mode
DOUT Edge
SCLK
↓
DIN Edge
SCLK
↑
1, 2
Resetting the Serial Interface
When writing to the part via the DIN line there is the possibility
of writing data into the incorrect registers, such as the test regis-
ter for instance, or writing the incorrect data and corrupting the
serial interface. The
SYNC
pin acts as a reset. Bringing the
SYNC
pin high resets the internal shift register. The first data
bit after the next
SYNC
falling edge will now be the first bit of a
new 16-bit transfer. It is also possible that the test register con-
tents were altered when the interface was lost. Therefore, once
the serial interface is reset it may be necessary to write the 16-bit
word 0100 0000 0000 0010 to restore the test register to its
default value. Now the part and serial interface are completely
reset. It is always useful to retain the ability to program the
SYNC
line from a port of the
μ
Controller/DSP to have the abil-
ity to reset the serial interface.
Table X summarizes the interface modes provided by the
AD7856. It also outlines the various
μ
P/
μ
C to which the par-
ticular interface is suited.
Interface Mode 1 may only be set by programming the control
register (See section on Control Register).
Some of the more popular
μ
Processors,
μ
Controllers, and DSP
machines that the AD7856 will interface to directly are men-
tioned here. This does not cover all
μ
Cs,
μ
Ps and DSPs. A more
detailed timing description on each of the interface modes follows.
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