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參數(shù)資料
| 型號： | AD7853ANZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/34頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SRL 200KSPS 24-DIP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 15 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 8051，QSPI?，串行，SPI? µP |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 33mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 24-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 24-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個偽差分，單極；1 個偽差分，雙極 |
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REV. B
–5–
AD7853/AD7853L
TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams.
Figure 2 shows the reading and writing after conversion in In-
terface Modes 2 and 3. To attain the maximum sample rate of
100 kHz (AD7853L) or 200 kHz (AD7853) in Interface Modes
2 and 3, reading and writing must be performed during conver-
sion. Figure 3 shows the timing diagram for Interface Modes 4
and 5 with sample rate of 100 kHz (AD7853L) or 200 kHz
(AD7853). At least 400 ns acquisition time must be allowed
(the time from the falling edge of BUSY to the next rising edge
of
CONVST) before the next conversion begins to ensure that
the part is settled to the 12-bit level. If the user does not want to
provide the
CONVST signal, the conversion can be initiated in
software by writing to the control register.
TO OUTPUT
PIN
+2.1V
IOH
1.6mA
200 A
IOL
CL
100pF
Figure 1. Load Circuit for Digital Output Timing
Specifications
POLARITY PIN LOGIC HIGH
SYNC (I/P)
SCLK (I/P)
t
3
BUSY (O/P)
CONVST (I/P)
t
2
t
1
t
5
t
11
t
6
t
9
t
10
15
6
16
t
12
t
6
DOUT (O/P)
DB0
DB11
t
8
DB15
DB0
THREE-
STATE
DB11
THREE-
STATE
DB15
t
CONVERT
t
7
t
CONVERT = 4.6 s MAX, 10 s FOR L VERSION
t
1 = 100 ns MIN, t5 = 50/90 ns MAX 5V/3V, t7 = 40/60 ns MIN 5V/3V
Figure 2. AD7853/AD7853L Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)
POLARITY PIN LOGIC HIGH
SYNC (O/P)
DOUT (O/P)
SCLK (O/P)
DB0
DB11
t
4
t
8
DIN (I/P)
DB15
DB0
THREE-
STATE
BUSY (O/P)
CONVST (I/P)
DB11
t
2
t
1
t
7
t
11
t
6
t
9
t
10
THREE-
STATE
15
6
16
t
12
t
5
DB15
t
CONVERT
t
CONVERT = 4.6 s MAX, 10 s FOR L VERSION
t
1 = 100 ns MIN, t5 = 50/90 ns MAX 5V/3V, t7 = 40/60 ns MIN 5V/3V
Figure 3. AD7853/AD7853L Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7853AR | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Serial 24-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:SELF CAL.SERIAL 12-BIT ADC I.C. - Bulk |
| AD7853AR-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Serial 24-Pin SOIC W T/R |
| AD7853ARS | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Serial 24-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:SELF CAL.SERIAL 12-BIT ADC I.C. - Bulk |
| AD7853ARS-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Serial 24-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:SELF CAL.SERIAL 12-BIT ADC I.C. - Tape and Reel |
| AD7853ARS-REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 200ksps 12-bit Serial 24-Pin SSOP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 200KSPS 12-BIT SERL 24SSOP - Tape and Reel |
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