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參數(shù)資料
| 型號： | AD7837 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Complete, Dual 12-Bit MDACs(完備的雙12位乘法D/A轉(zhuǎn)換器) |
| 中文描述： | 完備的雙12位醫(yī)療儀器行政管理制度（完備的雙12位乘法的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 280K |
| 代理商： | AD7837 |
AD7837/AD7847
REV. 0
–7–
CIRCUIT INFORMAT ION
D/A SE CT ION
A simplified circuit diagram for one of the D/A converters and
output amplifier is shown in Figure 1.
A segmented scheme is used whereby the 2 MSBs of the 12-bit
data word are decoded to drive the three switches A-C. T he re-
maining 10 bits drive the switches (S0–S9) in a standard R-2R
ladder configuration.
Each of the switches A–C steers 1/4 of the total reference cur-
rent with the remaining 1/4 passing through the R-2R section.
T he output amplifier and feedback resistor perform the current
to voltage conversion giving
V
OUT
= –
D
×
V
REF
where
D
is the fractional representation of the digital word. (
D
can be set from 0 to 4095/4096.)
T he output amplifier can maintain
±
10 V across a 2 k
load. It
is internally compensated and settles to 0.01% FSR (1/2 LSB)
in less than 5
μ
s. Note that on the AD7837, V
OUT
must be con-
nected externally to R
FB
.
R
R
R
2R
2R
2R
2R
2R
2R
B
A
S9
2R
C
V
REF
S8
S0
R/2
AGND
SHOWN FOR ALL 1s ON DAC
V
OUT
Figure 1. D/A Simplified Circuit Diagram
INT E RFACE LOGIC INFORMAT ION—AD7847
T he input control logic for the AD7847 is shown in Figure 2.
T he part contains a 12-bit latch for each DAC. It can be treated
as two independent DACs, each with its own
CS
input and a
common
WR
input.
CSA
and
WR
control the loading of data to
the DAC A latch, while
CSB
and
WR
control the loading of the
DAC B latch. T he latches are edge triggered so that input data
is latched to the respective latch on the rising edge of
WR
. If
CSA
and
CSB
are both low and
WR
is taken high, the same
data will be latched to both DAC latches. T he control logic
truth table is shown in T able I, while the write cycle timing dia-
gram for the part is shown in Figure 3.
DAC A LATCH
DAC B LATCH
CSA
WR
CSB
Figure 2. AD7847 Input Control Logic
T able I. AD7847 T ruth T able
CSA
CSB
WR
Function
X
1
0
1
0
g
1
g
X
1
1
0
0
1
g
g
1
X
g
g
g
0
0
0
No Data T ransfer
No Data T ransfer
Data Latched to DAC A
Data Latched to DAC B
Data Latched to Both DACs
Data Latched to DAC A
Data Latched to DAC B
Data Latched to Both DACs
X = Don’t Care.
g
= Rising Edge T riggered.
CSA, CSB
WR
DATA
VALID
DATA
t
1
t
3
t
2
t
4
t
5
Figure 3. AD7847 Write Cycle Timing Diagram
INT E RFACE LOGIC INFORMAT ION—AD7837
T he input loading structure on the AD7837 is configured for in-
terfacing to microprocessors with an 8-bit-wide data bus. T he
part contains two 12-bit latches per DAC—an input latch and a
DAC latch. Each input latch is further subdivided into a least-
significant 8-bit latch and a most-significant 4-bit latch. Only the
data held in the DAC latches determines the outputs from the
part. T he input control logic for the AD7837 is shown in Figure
4, while the write cycle timing diagram is shown in Figure 5.
DAC A LATCH
DAC A MS
INPUT
LATCH
DAC A LS
INPUT
LATCH
DAC B LATCH
DAC B MS
INPUT
LATCH
DAC B LS
INPUT
LATCH
12
12
4
4
8
8
8
DB7
DB0
LDAC
CS
WR
A0
A1
Figure 4. AD7837 Input Control Logic
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| AD7837AN | 功能描述:IC DAC 12BIT MULT DUAL 24-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD7837AN/883B | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Complete, Dual 12-Bit MDACs |
| AD7837AN883B | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Complete, Dual 12-Bit MDACs |
| AD7837AN-883B | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Complete, Dual 12-Bit MDACs |
| AD7837ANN | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Complete, Dual 12-Bit MDACs |
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