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參數(shù)資料
| 型號： | AD7829BRW-1RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT 8CH 2MSPS 28-SOIC |
| 標準包裝： | 400 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 36mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極 |
AD7829-1
Rev. 0 | Page 15 of 20
OPERATING MODES
Figure 19 shows the power vs. throughput rate for automatic,
full power-down.
The AD7829-1 has two possible modes of operation, depending
on the state of the CONVST pulse approximately 100 ns after the
end of a conversion, that is, upon the rising edge of the
THROUGHPUT (kSPS)
100
10
0
5
0100
PO
W
E
R
(m
W
)
1
200
300
400
0.1
50
150
250
350
450
06
17
9-
0
20
EOC pulse.
Mode 1 Operation (High-Speed Sampling)
When the AD7829-1 is operated in Mode 1, it is not powered
down between conversions. This mode of operation allows high
throughput rates to be achieved. Figure 21 shows how this
optimum throughput rate is achieved by bringing CONVST
high before the end of a conversion, that is, before the EOC
pulses low. When operating in this mode, a new conversion
should not be initiated until 30 ns after the end of a read
operation. This allows the track/hold to acquire the analog
signal to 0.5 LSB accuracy.
Mode 2 Operation (Automatic Power-Down)
Figure 19. AD7829-1 Power vs. Throughput
When the AD7829-1 is operated in Mode 2 (see Figure 22), it
automatically powers down at the end of a conversion. The
FREQUENCY (kHz)
0
–10
–80
(dB
)
–40
–50
–60
–70
–20
–30
0
113 14
2
170 198 22
7
255 283 31
2
34
0
368 396 42
5
453 481 51
0
53
8
566 595 62
3
651 680 70
8
73
6
765 793 82
1
850 878 90
6
93
5
963
28 57 85
991
2048 POINT FFT
SAMPLING
2MSPS
fIN = 200kHz
0
617
9-
0
21
CONVST signal is brought low to initiate a conversion and is
left logic low until after the EOC goes high, that is, approximately
100 ns after the end of the conversion. The state of the CONVST
signal is sampled at this point (that is, 530 ns maximum after
CONVST falling edge) and the AD7829-1 powers down as long
as CONVST is low. The ADC is powered up again on the rising
edge of the CONVST signal. Superior power performance can
be achieved in this mode of operation by powering up the
AD7829-1 only to carry out a conversion. The parallel interface
of the AD7829-1 is still fully operational while the ADCs are
powered down. A read can occur while the part is powered
down, and so it does not necessarily need to be placed within
the
Figure 20. AD7829-1 SNR
EOC pulse, as shown in Figure 22.
t2
t1
t3
VALID
DATA
CONVST
EOC
CS
RD
DB0 TO DB7
TRACK
HOLD
TRACK
HOLD
120ns
06
17
9-
0
22
Figure 21. Mode 1 Operation
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