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參數(shù)資料
| 型號(hào)： | AD7823YRZ-REEL7 |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT SRL 2.7-5.5V 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 17.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類(lèi)型： | 2 個(gè)偽差分，單極 |
AD7823
–3–
REV. C
TIMING CHARACTERISTICS
1, 2
Parameter
VDD = 5 V
10%
VDD = 3 V
10%
Unit
Conditions/Comments
t1
55
s (max)
Conversion Time Mode 1 Operation (High Speed Mode)
t2
20
ns (min)
CONVST Pulsewidth
t3
25
ns (min)
SCLK High Pulsewidth
t4
25
ns (min)
SCLK Low Pulsewidth
t5
3
5
ns (min)
CONVST Rising Edge to SCLK Rising Edge Set-Up Time
t6
3
10
ns (max)
SCLK Rising Edge to DOUT Data Valid Delay
t7
3
5
ns (max)
Data Hold Time after Rising Edge SCLK
t8
3, 4
20
ns (max)
Bus Relinquish Time after Falling Edge of SCLK
10
ns (min)
tPOWERUP
1.5
s (max)
Power-Up Time
NOTES
1Sample tested to ensure compliance.
2See Figures 14, 15 and 16.
3These numbers are measured with the load circuit of Figure 1. They are defined as the time required for the o/p to cross 0.8 V or 2.4 V for V
DD = 5 V
± 10% and
0.4 V or 2 V for VDD = 3 V
± 10%.
4Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the Timing Characteristics, t8, is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
(–40 C to +125 C, unless otherwise noted)
ABSOLUTE MAXIMUM RATINGS
*
(TA = 25
°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND
(
CONVST, SCLK) . . . . . . . . . . . . . . –0.3 V, V
DD + 0.3 V
Digital Output Voltage to GND
(DOUT) . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Analog Inputs
(VIN+, VIN–) . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
Storage Temperature Range . . . . . . . . . . . . –65
°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150
°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 125°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 50°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . 260
°C
IOL
200mA
IOH
200 A
1.6V
CL
50pF
TO
OUTPUT
PIN
Figure 1. Load Circuit for Digital Output Timing Specifications
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 160°C/W
θ
JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 56
°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215
°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
°C
MicroSOIC Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W
θ
JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44
°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215
°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Linearity
Temperature
Branding
Package
Model
Error
Range
Information
Option
*
AD7823YN
±1 LSB
–40
°C to +125°C
N-8
AD7823YR
±1 LSB
–40
°C to +125°C
SO-8
AD7823YRM
±1 LSB
–40
°C to +125°C
C2Y
RM-8
*N = plastic DIP; RM = microSOIC; SO = small outline IC (SOIC).
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